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MN10300: Cache: Split cache bits out of arch Kconfig
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Split the cache bits out of arch/mn10300/Kconfig as they're quite complex.

Signed-off-by: David Howells <dhowells@redhat.com>
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David Howells committed Oct 27, 2010
1 parent 86c0f93 commit 0bc42d7
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Showing 2 changed files with 33 additions and 28 deletions.
29 changes: 1 addition & 28 deletions arch/mn10300/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -136,34 +136,7 @@ config FPU
default y
depends on MN10300_PROC_MN103E010

choice
prompt "CPU Caching mode"
default MN10300_CACHE_WBACK
help
This option determines the caching mode for the kernel.

Write-Back caching mode involves the all reads and writes causing
the affected cacheline to be read into the cache first before being
operated upon. Memory is not then updated by a write until the cache
is filled and a cacheline needs to be displaced from the cache to
make room. Only at that point is it written back.

Write-Through caching only fetches cachelines from memory on a
read. Writes always get written directly to memory. If the affected
cacheline is also in cache, it will be updated too.

The final option is to turn of caching entirely.

config MN10300_CACHE_WBACK
bool "Write-Back"

config MN10300_CACHE_WTHRU
bool "Write-Through"

config MN10300_CACHE_DISABLED
bool "Disabled"

endchoice
source "arch/mn10300/mm/Kconfig.cache"

menu "Memory layout options"

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32 changes: 32 additions & 0 deletions arch/mn10300/mm/Kconfig.cache
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@@ -0,0 +1,32 @@
#
# MN10300 CPU cache options
#

choice
prompt "CPU Caching mode"
default MN10300_CACHE_WBACK
help
This option determines the caching mode for the kernel.

Write-Back caching mode involves the all reads and writes causing
the affected cacheline to be read into the cache first before being
operated upon. Memory is not then updated by a write until the cache
is filled and a cacheline needs to be displaced from the cache to
make room. Only at that point is it written back.

Write-Through caching only fetches cachelines from memory on a
read. Writes always get written directly to memory. If the affected
cacheline is also in cache, it will be updated too.

The final option is to turn of caching entirely.

config MN10300_CACHE_WBACK
bool "Write-Back"

config MN10300_CACHE_WTHRU
bool "Write-Through"

config MN10300_CACHE_DISABLED
bool "Disabled"

endchoice

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