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yaml
---
r: 28302
b: refs/heads/master
c: c32ba30
h: refs/heads/master
v: v3
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Paul Serice authored and Greg Kroah-Hartman committed Jun 21, 2006
1 parent 7d62515 commit 0bdcf3c
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Showing 2 changed files with 25 additions and 16 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: a5117ba7da37deb09df5eb802dace229b3fb1e9f
refs/heads/master: c32ba30f76eb18b3d4449072fe9c345a9574796b
39 changes: 24 additions & 15 deletions trunk/drivers/usb/host/ehci-pci.c
Original file line number Diff line number Diff line change
Expand Up @@ -76,6 +76,30 @@ static int ehci_pci_setup(struct usb_hcd *hcd)
dbg_hcs_params(ehci, "reset");
dbg_hcc_params(ehci, "reset");

/* ehci_init() causes memory for DMA transfers to be
* allocated. Thus, any vendor-specific workarounds based on
* limiting the type of memory used for DMA transfers must
* happen before ehci_init() is called. */
switch (pdev->vendor) {
case PCI_VENDOR_ID_NVIDIA:
/* NVidia reports that certain chips don't handle
* QH, ITD, or SITD addresses above 2GB. (But TD,
* data buffer, and periodic schedule are normal.)
*/
switch (pdev->device) {
case 0x003c: /* MCP04 */
case 0x005b: /* CK804 */
case 0x00d8: /* CK8 */
case 0x00e8: /* CK8S */
if (pci_set_consistent_dma_mask(pdev,
DMA_31BIT_MASK) < 0)
ehci_warn(ehci, "can't enable NVidia "
"workaround for >2GB RAM\n");
break;
}
break;
}

/* cache this readonly data; minimize chip reads */
ehci->hcs_params = readl(&ehci->caps->hcs_params);

Expand All @@ -88,8 +112,6 @@ static int ehci_pci_setup(struct usb_hcd *hcd)
if (retval)
return retval;

/* NOTE: only the parts below this line are PCI-specific */

switch (pdev->vendor) {
case PCI_VENDOR_ID_TDI:
if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
Expand All @@ -107,19 +129,6 @@ static int ehci_pci_setup(struct usb_hcd *hcd)
break;
case PCI_VENDOR_ID_NVIDIA:
switch (pdev->device) {
/* NVidia reports that certain chips don't handle
* QH, ITD, or SITD addresses above 2GB. (But TD,
* data buffer, and periodic schedule are normal.)
*/
case 0x003c: /* MCP04 */
case 0x005b: /* CK804 */
case 0x00d8: /* CK8 */
case 0x00e8: /* CK8S */
if (pci_set_consistent_dma_mask(pdev,
DMA_31BIT_MASK) < 0)
ehci_warn(ehci, "can't enable NVidia "
"workaround for >2GB RAM\n");
break;
/* Some NForce2 chips have problems with selective suspend;
* fixed in newer silicon.
*/
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