ASoC: Fix FLL reference clock division setup in WM8993

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
git-mirror · Jul 17, 2009 · 0c11f65 · 0c11f65
1 parent 8aa2df5
commit 0c11f65
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/sound/soc/codecs/wm8993.c b/sound/soc/codecs/wm8993.c
@@ -345,8 +345,10 @@ static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
 
 	/* Fref must be <=13.5MHz */
 	div = 1;
+	fll_div->fll_clk_ref_div = 0;
 	while ((Fref / div) > 13500000) {
 		div *= 2;
+		fll_div->fll_clk_ref_div++;
 
 		if (div > 8) {
 			pr_err("Can't scale %dMHz input down to <=13.5MHz\n",