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yaml
---
r: 295725
b: refs/heads/master
c: 44b2cef
h: refs/heads/master
i:
  295723: fb7e1e2
v: v3
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MyungJoo Ham authored and Kukjin Kim committed Mar 11, 2012
1 parent 0827ed1 commit 0c5f527
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2 changes: 1 addition & 1 deletion [refs]
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---
refs/heads/master: d074de8ef5a8b241c129690014138fcadcd72bc4
refs/heads/master: 44b2cef5ae6da48523fa634230ca66107110a7dd
43 changes: 43 additions & 0 deletions trunk/arch/arm/mach-exynos/include/mach/regs-clock.h
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Expand Up @@ -77,6 +77,7 @@
#define EXYNOS4_CLKDIV2_RATIO EXYNOS_CLKREG(0x0C580)

#define EXYNOS4_CLKDIV_STAT_TOP EXYNOS_CLKREG(0x0C610)
#define EXYNOS4_CLKDIV_STAT_MFC EXYNOS_CLKREG(0x0C628)

#define EXYNOS4_CLKGATE_SCLKCAM EXYNOS_CLKREG(0x0C820)
#define EXYNOS4_CLKGATE_IP_CAM EXYNOS_CLKREG(0x0C920)
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#define EXYNOS4_CLKDIV_DMC0 EXYNOS_CLKREG(0x10500)
#define EXYNOS4_CLKDIV_DMC1 EXYNOS_CLKREG(0x10504)
#define EXYNOS4_CLKDIV_STAT_DMC0 EXYNOS_CLKREG(0x10600)
#define EXYNOS4_CLKDIV_STAT_DMC1 EXYNOS_CLKREG(0x10604)
#define EXYNOS4_CLKGATE_IP_DMC EXYNOS_CLKREG(0x10900)

#define EXYNOS4_DMC_PAUSE_CTRL EXYNOS_CLKREG(0x11094)
#define EXYNOS4_DMC_PAUSE_ENABLE (1 << 0)

#define EXYNOS4_APLL_LOCK EXYNOS_CLKREG(0x14000)
#define EXYNOS4_MPLL_LOCK (soc_is_exynos4210() ? \
EXYNOS_CLKREG(0x14004) : \
Expand Down Expand Up @@ -187,6 +192,22 @@
#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28)
#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)

#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT (0)
#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT)
#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT (4)
#define EXYNOS4_CLKDIV_DMC1_C2C_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT)
#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT (8)
#define EXYNOS4_CLKDIV_DMC1_PWI_MASK (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT)
#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT (12)
#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)
#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT (16)
#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT)
#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT (24)
#define EXYNOS4_CLKDIV_DMC1_DPM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT)

#define EXYNOS4_CLKDIV_MFC_SHIFT (0)
#define EXYNOS4_CLKDIV_MFC_MASK (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT)

#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0)
#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)
#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4)
Expand All @@ -197,19 +218,41 @@
#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)
#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16)
#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)
#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT (20)
#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT)
#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24)
#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT)

#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0)
#define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)
#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4)
#define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)

#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT (0)
#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT)
#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT (4)
#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT)
#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT (8)
#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT)
#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT (12)
#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)

/* Only for EXYNOS4210 */

#define EXYNOS4210_CLKSRC_LCD1 EXYNOS_CLKREG(0x0C238)
#define EXYNOS4210_CLKSRC_MASK_LCD1 EXYNOS_CLKREG(0x0C338)
#define EXYNOS4210_CLKDIV_LCD1 EXYNOS_CLKREG(0x0C538)
#define EXYNOS4210_CLKGATE_IP_LCD1 EXYNOS_CLKREG(0x0C938)

/* Only for EXYNOS4212 */

#define EXYNOS4_CLKDIV_CAM1 EXYNOS_CLKREG(0x0C568)

#define EXYNOS4_CLKDIV_STAT_CAM1 EXYNOS_CLKREG(0x0C668)

#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)
#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)

/* Compatibility defines and inclusion */

#include <mach/regs-pmu.h>
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