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yaml
---
r: 295084
b: refs/heads/master
c: 23bfb5b
h: refs/heads/master
v: v3
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Andrew Miller authored and Mauro Carvalho Chehab committed Mar 19, 2012
1 parent c63a5f7 commit 0ce278b
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Showing 2 changed files with 17 additions and 17 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 68a6bb546575a2ba62baddbde710fac42ff04f19
refs/heads/master: 23bfb5be9f4c14937d70ed09f24a19d86df1951b
32 changes: 16 additions & 16 deletions trunk/drivers/staging/media/solo6x10/core.c
Original file line number Diff line number Diff line change
Expand Up @@ -195,28 +195,28 @@ static int __devinit solo_pci_probe(struct pci_dev *pdev,
SOLO6010_SYS_CFG_OUTDIV(3);
solo_reg_write(solo_dev, SOLO_SYS_CFG, reg);

if (solo_dev->flags & FLAGS_6110) {
u32 sys_clock_MHz = SOLO_CLOCK_MHZ;
u32 pll_DIVQ;
u32 pll_DIVF;

if (sys_clock_MHz < 125) {
pll_DIVQ = 3;
pll_DIVF = (sys_clock_MHz * 4) / 3;
} else {
pll_DIVQ = 2;
pll_DIVF = (sys_clock_MHz * 2) / 3;
}

solo_reg_write(solo_dev, SOLO6110_PLL_CONFIG,
if (solo_dev->flags & FLAGS_6110) {
u32 sys_clock_MHz = SOLO_CLOCK_MHZ;
u32 pll_DIVQ;
u32 pll_DIVF;

if (sys_clock_MHz < 125) {
pll_DIVQ = 3;
pll_DIVF = (sys_clock_MHz * 4) / 3;
} else {
pll_DIVQ = 2;
pll_DIVF = (sys_clock_MHz * 2) / 3;
}

solo_reg_write(solo_dev, SOLO6110_PLL_CONFIG,
SOLO6110_PLL_RANGE_5_10MHZ |
SOLO6110_PLL_DIVR(9) |
SOLO6110_PLL_DIVQ_EXP(pll_DIVQ) |
SOLO6110_PLL_DIVF(pll_DIVF) | SOLO6110_PLL_FSEN);
mdelay(1); // PLL Locking time (1ms)
mdelay(1); /* PLL Locking time (1ms) */

solo_reg_write(solo_dev, SOLO_DMA_CTRL1, 3 << 8); /* ? */
} else
} else
solo_reg_write(solo_dev, SOLO_DMA_CTRL1, 1 << 8); /* ? */

solo_reg_write(solo_dev, SOLO_TIMER_CLOCK_NUM, SOLO_CLOCK_MHZ - 1);
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