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gma500: tidy up the CDV files
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We are close to having PSB and CDV ready for moving from staging so it's
time to get the polish out.

Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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Alan Cox authored and Greg Kroah-Hartman committed Jul 8, 2011
1 parent 2b9428e commit 0cf0db5
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Showing 5 changed files with 133 additions and 126 deletions.
21 changes: 11 additions & 10 deletions drivers/staging/gma500/cdv_device.c
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Original file line number Diff line number Diff line change
Expand Up @@ -129,7 +129,6 @@ static int cdv_backlight_setup(struct drm_device *dev)

static int cdv_set_brightness(struct backlight_device *bd)
{
struct drm_device *dev = bl_get_data(cdv_backlight_device);
int level = bd->props.brightness;

/* Percentage 1-100% being valid */
Expand Down Expand Up @@ -188,19 +187,19 @@ static inline u32 CDV_MSG_READ32(uint port, uint offset)
{
int mcr = (0x10<<24) | (port << 16) | (offset << 8);
uint32_t ret_val = 0;
struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
pci_write_config_dword (pci_root, 0xD0, mcr);
pci_read_config_dword (pci_root, 0xD4, &ret_val);
struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
pci_write_config_dword(pci_root, 0xD0, mcr);
pci_read_config_dword(pci_root, 0xD4, &ret_val);
pci_dev_put(pci_root);
return ret_val;
}

static inline void CDV_MSG_WRITE32(uint port, uint offset, u32 value)
{
int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
pci_write_config_dword (pci_root, 0xD4, value);
pci_write_config_dword (pci_root, 0xD0, mcr);
struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
pci_write_config_dword(pci_root, 0xD4, value);
pci_write_config_dword(pci_root, 0xD0, mcr);
pci_dev_put(pci_root);
}

Expand All @@ -218,8 +217,10 @@ static void cdv_init_pm(struct drm_device *dev)
u32 pwr_cnt;
int i;

dev_priv->apm_base = CDV_MSG_READ32(PSB_PUNIT_PORT, PSB_APMBA) & 0xFFFF;
dev_priv->ospm_base = CDV_MSG_READ32(PSB_PUNIT_PORT, PSB_OSPMBA) & 0xFFFF;
dev_priv->apm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
PSB_APMBA) & 0xFFFF;
dev_priv->ospm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
PSB_OSPMBA) & 0xFFFF;

/* Force power on for now */
pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
Expand Down Expand Up @@ -346,5 +347,5 @@ const struct psb_ops cdv_chip_ops = {
.save_regs = cdv_save_display_registers,
.restore_regs = cdv_restore_display_registers,
.power_down = cdv_power_down,
.power_up = cdv_power_up,
.power_up = cdv_power_up,
};
23 changes: 13 additions & 10 deletions drivers/staging/gma500/cdv_intel_crt.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -45,7 +45,7 @@ static void cdv_intel_crt_dpms(struct drm_encoder *encoder, int mode)
temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
temp &= ~ADPA_DAC_ENABLE;

switch(mode) {
switch (mode) {
case DRM_MODE_DPMS_ON:
temp |= ADPA_DAC_ENABLE;
break;
Expand Down Expand Up @@ -128,11 +128,10 @@ static void cdv_intel_crt_mode_set(struct drm_encoder *encoder,
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
adpa |= ADPA_VSYNC_ACTIVE_HIGH;

if (psb_intel_crtc->pipe == 0) {
if (psb_intel_crtc->pipe == 0)
adpa |= ADPA_PIPE_A_SELECT;
} else {
else
adpa |= ADPA_PIPE_B_SELECT;
}

REG_WRITE(adpa_reg, adpa);
}
Expand All @@ -144,7 +143,8 @@ static void cdv_intel_crt_mode_set(struct drm_encoder *encoder,
* \return true if CRT is connected.
* \return false if CRT is disconnected.
*/
static bool cdv_intel_crt_detect_hotplug(struct drm_connector *connector, bool force)
static bool cdv_intel_crt_detect_hotplug(struct drm_connector *connector,
bool force)
{
struct drm_device *dev = connector->dev;
u32 hotplug_en;
Expand Down Expand Up @@ -193,7 +193,8 @@ static bool cdv_intel_crt_detect_hotplug(struct drm_connector *connector, bool f
return ret;
}

static enum drm_connector_status cdv_intel_crt_detect(struct drm_connector *connector, bool force)
static enum drm_connector_status cdv_intel_crt_detect(
struct drm_connector *connector, bool force)
{
if (cdv_intel_crt_detect_hotplug(connector, force))
return connector_status_connected;
Expand Down Expand Up @@ -245,7 +246,8 @@ static const struct drm_connector_funcs cdv_intel_crt_connector_funcs = {
.set_property = cdv_intel_crt_set_property,
};

static const struct drm_connector_helper_funcs cdv_intel_crt_connector_helper_funcs = {
static const struct drm_connector_helper_funcs
cdv_intel_crt_connector_helper_funcs = {
.mode_valid = cdv_intel_crt_mode_valid,
.get_modes = cdv_intel_crt_get_modes,
.best_encoder = psb_intel_best_encoder,
Expand Down Expand Up @@ -277,11 +279,11 @@ void cdv_intel_crt_init(struct drm_device *dev,
psb_intel_output->mode_dev = mode_dev;
connector = &psb_intel_output->base;
drm_connector_init(dev, connector,
&cdv_intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
&cdv_intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);

encoder = &psb_intel_output->enc;
drm_encoder_init(dev, encoder,
&cdv_intel_crt_enc_funcs, DRM_MODE_ENCODER_DAC);
&cdv_intel_crt_enc_funcs, DRM_MODE_ENCODER_DAC);

drm_mode_connector_attach_encoder(&psb_intel_output->base,
&psb_intel_output->enc);
Expand Down Expand Up @@ -310,7 +312,8 @@ void cdv_intel_crt_init(struct drm_device *dev,
connector->doublescan_allowed = 0;

drm_encoder_helper_add(encoder, &cdv_intel_crt_helper_funcs);
drm_connector_helper_add(connector, &cdv_intel_crt_connector_helper_funcs);
drm_connector_helper_add(connector,
&cdv_intel_crt_connector_helper_funcs);

drm_sysfs_connector_add(connector);

Expand Down
115 changes: 55 additions & 60 deletions drivers/staging/gma500/cdv_intel_display.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
*
* Authors:
Expand Down Expand Up @@ -40,8 +40,7 @@ struct cdv_intel_p2_t {
int p2_slow, p2_fast;
};

struct cdv_intel_clock_t
{
struct cdv_intel_clock_t {
/* given values */
int n;
int m1, m2;
Expand Down Expand Up @@ -117,17 +116,18 @@ static const struct cdv_intel_limit_t cdv_intel_limits[] = {
};

#define _wait_for(COND, MS, W) ({ \
unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
int ret__ = 0; \
while (! (COND)) { \
if (time_after(jiffies, timeout__)) { \
ret__ = -ETIMEDOUT; \
break; \
} \
if (W && !in_dbg_master()) msleep(W); \
} \
ret__; \
})
unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
int ret__ = 0; \
while (!(COND)) { \
if (time_after(jiffies, timeout__)) { \
ret__ = -ETIMEDOUT; \
break; \
} \
if (W && !in_dbg_master()) \
msleep(W); \
} \
ret__; \
})

#define wait_for(COND, MS) _wait_for(COND, MS, 1)

Expand Down Expand Up @@ -237,7 +237,7 @@ cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
ref_value = 0x68A701;

cdv_sb_write(dev, SB_REF_SFR(pipe), ref_value);

/* We don't know what the other fields of these regs are, so
* leave them in place.
*/
Expand Down Expand Up @@ -324,14 +324,13 @@ cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
lane_value |= LANE_PLL_ENABLE;
cdv_sb_write(dev, lane_reg, lane_value);

/* Program the Lane2/3 for HDMI C */
/* Program the Lane2/3 for HDMI C */
lane_reg = PSB_LANE2;
cdv_sb_read(dev, lane_reg, &lane_value);
lane_value &= ~(LANE_PLL_MASK);
lane_value |= LANE_PLL_ENABLE;
cdv_sb_write(dev, lane_reg, lane_value);


lane_reg = PSB_LANE3;
cdv_sb_read(dev, lane_reg, &lane_value);
lane_value &= ~(LANE_PLL_MASK);
Expand Down Expand Up @@ -362,17 +361,18 @@ bool cdv_intel_pipe_has_type(struct drm_crtc *crtc, int type)
return false;
}

static const struct cdv_intel_limit_t *cdv_intel_limit(struct drm_crtc *crtc, int refclk)
static const struct cdv_intel_limit_t *cdv_intel_limit(struct drm_crtc *crtc,
int refclk)
{
const struct cdv_intel_limit_t *limit;
if (cdv_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
/*
* Now only single-channel LVDS is supported on CDV. If it is
* incorrect, please add the dual-channel LVDS.
*/
* Now only single-channel LVDS is supported on CDV. If it is
* incorrect, please add the dual-channel LVDS.
*/
if (refclk == 96000)
limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_96];
else
else
limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_100];
} else {
if (refclk == 27000)
Expand All @@ -384,7 +384,7 @@ static const struct cdv_intel_limit_t *cdv_intel_limit(struct drm_crtc *crtc, in
}

/* m1 is reserved as 0 in CDV, n is a ring counter */
static void cdv_intel_clock(struct drm_device *dev,
static void cdv_intel_clock(struct drm_device *dev,
int refclk, struct cdv_intel_clock_t *clock)
{
clock->m = clock->m2 + 2;
Expand Down Expand Up @@ -448,19 +448,22 @@ static bool cdv_intel_find_best_PLL(struct drm_crtc *crtc, int target,

memset(best_clock, 0, sizeof(*best_clock));
clock.m1 = 0;
/* m1 is reserved as 0 in CDV, n is a ring counter. So skip the m1 loop */
/* m1 is reserved as 0 in CDV, n is a ring counter.
So skip the m1 loop */
for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max;
clock.m2++) {
for (clock.p1 = limit->p1.min; clock.p1 <= limit->p1.max;
clock.p1++) {
for (clock.p1 = limit->p1.min;
clock.p1 <= limit->p1.max;
clock.p1++) {
int this_err;

cdv_intel_clock(dev, refclk, &clock);

if (!cdv_intel_PLL_is_valid(crtc, limit, &clock))
if (!cdv_intel_PLL_is_valid(crtc,
limit, &clock))
continue;

this_err = abs(clock.dot - target);
if (this_err < err) {
*best_clock = clock;
Expand Down Expand Up @@ -533,7 +536,7 @@ int cdv_intel_pipe_set_base(struct drm_crtc *crtc,
REG_WRITE(dspcntr_reg, dspcntr);

dev_dbg(dev->dev,
"Writing base %08lX %08lX %d %d\n", start, offset, x, y);
"Writing base %08lX %08lX %d %d\n", start, offset, x, y);

REG_WRITE(dspbase, offset);
REG_READ(dspbase);
Expand Down Expand Up @@ -808,7 +811,7 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
dpll |= DPLLB_MODE_LVDS;
else
dpll |= DPLLB_MODE_DAC_SERIAL;
//dpll |= (2 << 11);
/* dpll |= (2 << 11); */

/* setup pipeconf */
pipeconf = REG_READ(pipeconf_reg);
Expand All @@ -824,14 +827,12 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
dspcntr |= DISPLAY_PLANE_ENABLE;
pipeconf |= PIPEACONF_ENABLE;

REG_WRITE(dpll_reg,
dpll | DPLL_VGA_MODE_DIS |
DPLL_SYNCLOCK_ENABLE);
REG_READ(dpll_reg);
REG_WRITE(dpll_reg, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);
REG_READ(dpll_reg);

cdv_dpll_set_clock_cdv(dev, crtc, &clock);

udelay(150);
udelay(150);


/* The LVDS pin pair needs to be on before the DPLLs are enabled.
Expand Down Expand Up @@ -864,7 +865,6 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,

dpll |= DPLL_VCO_ENABLE;


/* Disable the panel fitter if it was on our pipe */
if (cdv_intel_panel_fitter_pipe(dev) == pipe)
REG_WRITE(PFIT_CONTROL, 0);
Expand All @@ -873,24 +873,19 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
drm_mode_debug_printmodeline(mode);

REG_WRITE(dpll_reg,
(REG_READ(dpll_reg) & ~DPLL_LOCK) |
DPLL_VCO_ENABLE);
REG_READ(dpll_reg);
(REG_READ(dpll_reg) & ~DPLL_LOCK) | DPLL_VCO_ENABLE);
REG_READ(dpll_reg);
/* Wait for the clocks to stabilize. */
udelay(150); /* 42 usec w/o calibration, 110 with. rounded up. */

if (!(REG_READ(dpll_reg) & DPLL_LOCK)) {
dev_err(dev->dev, "Failed to get DPLL lock\n");
return -EBUSY;
}

{
int sdvo_pixel_multiply =
adjusted_mode->clock / mode->clock;
REG_WRITE(dpll_md_reg,
(0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
((sdvo_pixel_multiply -
1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
udelay(150); /* 42 usec w/o calibration, 110 with. rounded up. */

if (!(REG_READ(dpll_reg) & DPLL_LOCK)) {
dev_err(dev->dev, "Failed to get DPLL lock\n");
return -EBUSY;
}

{
int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
REG_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
}

REG_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
Expand Down Expand Up @@ -956,10 +951,10 @@ void cdv_intel_crtc_load_lut(struct drm_crtc *crtc)
palreg = PALETTE_C;
break;
default:
dev_err(dev->dev, "Illegal Pipe Number. \n");
dev_err(dev->dev, "Illegal Pipe Number.\n");
return;
}

if (gma_power_begin(dev, false)) {
for (i = 0; i < 256; i++) {
REG_WRITE(palreg + 4 * i,
Expand Down Expand Up @@ -1276,7 +1271,7 @@ static int cdv_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
}

static void cdv_intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
u16 *green, u16 *blue, uint32_t start, uint32_t size)
u16 *green, u16 *blue, uint32_t start, uint32_t size)
{
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
int i;
Expand All @@ -1294,10 +1289,10 @@ static void cdv_intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
static int cdv_crtc_set_config(struct drm_mode_set *set)
{
int ret = 0;
struct drm_device * dev = set->crtc->dev;
struct drm_psb_private * dev_priv = dev->dev_private;
struct drm_device *dev = set->crtc->dev;
struct drm_psb_private *dev_priv = dev->dev_private;

if(!dev_priv->rpm_enabled)
if (!dev_priv->rpm_enabled)
return drm_crtc_helper_set_config(set);

pm_runtime_forbid(&dev->pdev->dev);
Expand Down Expand Up @@ -1489,7 +1484,7 @@ void cdv_intel_cursor_init(struct drm_device *dev, int pipe)
{
uint32_t control;
uint32_t base;

switch (pipe) {
case 0:
control = CURACNTR;
Expand Down
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