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yaml
---
r: 134279
b: refs/heads/master
c: 94ff91d
h: refs/heads/master
i:
  134277: 86b0f86
  134275: 9276a72
  134271: c79aadf
v: v3
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Sujith authored and John W. Linville committed Jan 30, 2009
1 parent 7bfb523 commit 0d86520
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Showing 2 changed files with 26 additions and 7 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: f46730d13f23b4578dca1c0f7663ea3093ff4f0e
refs/heads/master: 94ff91d4afd8ae14e8bb7012ba17cf6984130e44
31 changes: 25 additions & 6 deletions trunk/drivers/net/wireless/ath9k/mac.c
Original file line number Diff line number Diff line change
Expand Up @@ -107,14 +107,32 @@ bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel)

bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q)
{
#define ATH9K_TX_STOP_DMA_TIMEOUT 4000 /* usec */
#define ATH9K_TIME_QUANTUM 100 /* usec */

struct ath_hal_5416 *ahp = AH5416(ah);
struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
struct ath9k_tx_queue_info *qi;
u32 tsfLow, j, wait;
u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;

if (q >= pCap->total_queues) {
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q);
return false;
}

qi = &ahp->ah_txq[q];
if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n");
return false;
}

REG_WRITE(ah, AR_Q_TXD, 1 << q);

for (wait = 1000; wait != 0; wait--) {
for (wait = wait_time; wait != 0; wait--) {
if (ath9k_hw_numtxpending(ah, q) == 0)
break;
udelay(100);
udelay(ATH9K_TIME_QUANTUM);
}

if (ath9k_hw_numtxpending(ah, q)) {
Expand Down Expand Up @@ -144,24 +162,25 @@ bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q)
udelay(200);
REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);

wait = 1000;

wait = wait_time;
while (ath9k_hw_numtxpending(ah, q)) {
if ((--wait) == 0) {
DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
"Failed to stop Tx DMA in 100 "
"msec after killing last frame\n");
break;
}
udelay(100);
udelay(ATH9K_TIME_QUANTUM);
}

REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
}

REG_WRITE(ah, AR_Q_TXD, 0);

return wait != 0;

#undef ATH9K_TX_STOP_DMA_TIMEOUT
#undef ATH9K_TIME_QUANTUM
}

bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
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