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staging: brcm80211: replaced all volatile typedefs
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Volatile keyword is not needed, hardware is accessed using native Linux
calls that provide synchronization.

Signed-off-by: Roland Vossen <rvossen@broadcom.com>
Reviewed-by: Arend van Spriel <arend@broadcom.com>
Reviewed-by: Franky Lin <frankyl@broadcom.com>
Signed-off-by: Arend van Spriel <arend@broadcom.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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Roland Vossen authored and Greg Kroah-Hartman committed Aug 23, 2011
1 parent 786d00f commit 0da6491
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Showing 14 changed files with 157 additions and 156 deletions.
3 changes: 2 additions & 1 deletion drivers/staging/brcm80211/brcmfmac/dhd_sdio.c
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Original file line number Diff line number Diff line change
Expand Up @@ -475,7 +475,8 @@ BRCMF_SPINWAIT_SLEEP_INIT(sdioh_spinwait_sleep);
* Core reg address translation.
* Both macro's returns a 32 bits byte address on the backplane bus.
*/
#define CORE_CC_REG(base, field) (base + offsetof(chipcregs_t, field))
#define CORE_CC_REG(base, field) \
(base + offsetof(struct chipcregs, field))
#define CORE_BUS_REG(base, field) \
(base + offsetof(struct sdpcmd_regs, field))
#define CORE_SB(base, field) \
Expand Down
64 changes: 34 additions & 30 deletions drivers/staging/brcm80211/brcmsmac/aiutils.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -437,7 +437,7 @@ static void ai_hwfixup(struct si_info *sii)
void ai_scan(struct si_pub *sih, void *regs)
{
struct si_info *sii = SI_INFO(sih);
chipcregs_t *cc = (chipcregs_t *) regs;
struct chipcregs *cc = (struct chipcregs *) regs;
u32 erombase, *eromptr, *eromlim;

erombase = R_REG(&cc->eromptr);
Expand Down Expand Up @@ -854,8 +854,9 @@ static struct si_info *ai_doattach(struct si_info *sii, void *regs,
uint bustype, void *sdh, char **vars,
uint *varsz);
static bool ai_buscore_prep(struct si_info *sii, uint bustype);
static bool ai_buscore_setup(struct si_info *sii, chipcregs_t *cc, uint bustype,
u32 savewin, uint *origidx, void *regs);
static bool ai_buscore_setup(struct si_info *sii, struct chipcregs *cc,
uint bustype, u32 savewin, uint *origidx,
void *regs);
static void ai_nvram_process(struct si_info *sii, char *pvars);

/* dev path concatenation util */
Expand Down Expand Up @@ -910,8 +911,9 @@ static bool ai_buscore_prep(struct si_info *sii, uint bustype)
return true;
}

static bool ai_buscore_setup(struct si_info *sii, chipcregs_t *cc, uint bustype,
u32 savewin, uint *origidx, void *regs)
static bool
ai_buscore_setup(struct si_info *sii, struct chipcregs *cc, uint bustype,
u32 savewin, uint *origidx, void *regs)
{
bool pci, pcie;
uint i;
Expand Down Expand Up @@ -1074,7 +1076,7 @@ static struct si_info *ai_doattach(struct si_info *sii,
{
struct si_pub *sih = &sii->pub;
u32 w, savewin;
chipcregs_t *cc;
struct chipcregs *cc;
char *pvars = NULL;
uint socitype;
uint origidx;
Expand Down Expand Up @@ -1106,9 +1108,9 @@ static struct si_info *ai_doattach(struct si_info *sii,
savewin = SI_ENUM_BASE;
pci_write_config_dword(sii->pbus, PCI_BAR0_WIN,
SI_ENUM_BASE);
cc = (chipcregs_t *) regs;
cc = (struct chipcregs *) regs;
} else {
cc = (chipcregs_t *) REG_MAP(SI_ENUM_BASE, SI_CORE_SIZE);
cc = (struct chipcregs *) REG_MAP(SI_ENUM_BASE, SI_CORE_SIZE);
}

sih->bustype = bustype;
Expand Down Expand Up @@ -1167,7 +1169,7 @@ static struct si_info *ai_doattach(struct si_info *sii,
ai_nvram_process(sii, pvars);

/* === NVRAM, clock is ready === */
cc = (chipcregs_t *) ai_setcore(sih, CC_CORE_ID, 0);
cc = (struct chipcregs *) ai_setcore(sih, CC_CORE_ID, 0);
W_REG(&cc->gpiopullup, 0);
W_REG(&cc->gpiopulldown, 0);
ai_setcoreidx(sih, origidx);
Expand All @@ -1190,7 +1192,8 @@ static struct si_info *ai_doattach(struct si_info *sii,
w = getintvar(pvars, "leddc");
if (w == 0)
w = DEFAULT_GPIOTIMERVAL;
ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, gpiotimerval), ~0, w);
ai_corereg(sih, SI_CC_IDX, offsetof(struct chipcregs, gpiotimerval),
~0, w);

if (PCIE(sii)) {
pcicore_attach(sii->pch, pvars, SI_DOATTACH);
Expand All @@ -1204,7 +1207,7 @@ static struct si_info *ai_doattach(struct si_info *sii,
if (sih->chiprev == 0) {
SI_MSG(("Applying 43224A0 WARs\n"));
ai_corereg(sih, SI_CC_IDX,
offsetof(chipcregs_t, chipcontrol),
offsetof(struct chipcregs, chipcontrol),
CCTRL43224_GPIO_TOGGLE,
CCTRL43224_GPIO_TOGGLE);
si_pmu_chipcontrol(sih, 0, CCTRL_43224A0_12MA_LED_DRIVE,
Expand Down Expand Up @@ -1556,7 +1559,7 @@ void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits)
/* return the slow clock source - LPO, XTAL, or PCI */
static uint ai_slowclk_src(struct si_info *sii)
{
chipcregs_t *cc;
struct chipcregs *cc;
u32 val;

if (sii->pub.ccrev < 6) {
Expand All @@ -1568,7 +1571,7 @@ static uint ai_slowclk_src(struct si_info *sii)
}
return SCC_SS_XTAL;
} else if (sii->pub.ccrev < 10) {
cc = (chipcregs_t *) ai_setcoreidx(&sii->pub, sii->curidx);
cc = (struct chipcregs *) ai_setcoreidx(&sii->pub, sii->curidx);
return R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK;
} else /* Insta-clock */
return SCC_SS_XTAL;
Expand All @@ -1578,7 +1581,8 @@ static uint ai_slowclk_src(struct si_info *sii)
* return the ILP (slowclock) min or max frequency
* precondition: we've established the chip has dynamic clk control
*/
static uint ai_slowclk_freq(struct si_info *sii, bool max_freq, chipcregs_t *cc)
static uint
ai_slowclk_freq(struct si_info *sii, bool max_freq, struct chipcregs *cc)
{
u32 slowclk;
uint div;
Expand Down Expand Up @@ -1614,7 +1618,7 @@ static uint ai_slowclk_freq(struct si_info *sii, bool max_freq, chipcregs_t *cc)

static void ai_clkctl_setdelay(struct si_info *sii, void *chipcregs)
{
chipcregs_t *cc = (chipcregs_t *) chipcregs;
struct chipcregs *cc = (struct chipcregs *) chipcregs;
uint slowmaxfreq, pll_delay, slowclk;
uint pll_on_delay, fref_sel_delay;

Expand Down Expand Up @@ -1646,7 +1650,7 @@ void ai_clkctl_init(struct si_pub *sih)
{
struct si_info *sii;
uint origidx = 0;
chipcregs_t *cc;
struct chipcregs *cc;
bool fast;

if (!CCCTL_ENAB(sih))
Expand All @@ -1656,11 +1660,11 @@ void ai_clkctl_init(struct si_pub *sih)
fast = SI_FAST(sii);
if (!fast) {
origidx = sii->curidx;
cc = (chipcregs_t *) ai_setcore(sih, CC_CORE_ID, 0);
cc = (struct chipcregs *) ai_setcore(sih, CC_CORE_ID, 0);
if (cc == NULL)
return;
} else {
cc = (chipcregs_t *) CCREGS_FAST(sii);
cc = (struct chipcregs *) CCREGS_FAST(sii);
if (cc == NULL)
return;
}
Expand All @@ -1684,7 +1688,7 @@ u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih)
{
struct si_info *sii;
uint origidx = 0;
chipcregs_t *cc;
struct chipcregs *cc;
uint slowminfreq;
u16 fpdelay;
uint intr_val = 0;
Expand All @@ -1706,11 +1710,11 @@ u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih)
if (!fast) {
origidx = sii->curidx;
INTR_OFF(sii, intr_val);
cc = (chipcregs_t *) ai_setcore(sih, CC_CORE_ID, 0);
cc = (struct chipcregs *) ai_setcore(sih, CC_CORE_ID, 0);
if (cc == NULL)
goto done;
} else {
cc = (chipcregs_t *) CCREGS_FAST(sii);
cc = (struct chipcregs *) CCREGS_FAST(sii);
if (cc == NULL)
goto done;
}
Expand Down Expand Up @@ -1825,7 +1829,7 @@ bool ai_clkctl_cc(struct si_pub *sih, uint mode)
static bool _ai_clkctl_cc(struct si_info *sii, uint mode)
{
uint origidx = 0;
chipcregs_t *cc;
struct chipcregs *cc;
u32 scc;
uint intr_val = 0;
bool fast = SI_FAST(sii);
Expand All @@ -1843,9 +1847,9 @@ static bool _ai_clkctl_cc(struct si_info *sii, uint mode)
(ai_corerev(&sii->pub) <= 7) && (sii->pub.ccrev >= 10))
goto done;

cc = (chipcregs_t *) ai_setcore(&sii->pub, CC_CORE_ID, 0);
cc = (struct chipcregs *) ai_setcore(&sii->pub, CC_CORE_ID, 0);
} else {
cc = (chipcregs_t *) CCREGS_FAST(sii);
cc = (struct chipcregs *) CCREGS_FAST(sii);
if (cc == NULL)
goto done;
}
Expand Down Expand Up @@ -2164,21 +2168,21 @@ u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val, u8 priority)
val &= mask;
}

regoff = offsetof(chipcregs_t, gpiocontrol);
regoff = offsetof(struct chipcregs, gpiocontrol);
return ai_corereg(sih, SI_CC_IDX, regoff, mask, val);
}

void ai_chipcontrl_epa4331(struct si_pub *sih, bool on)
{
struct si_info *sii;
chipcregs_t *cc;
struct chipcregs *cc;
uint origidx;
u32 val;

sii = SI_INFO(sih);
origidx = ai_coreidx(sih);

cc = (chipcregs_t *) ai_setcore(sih, CC_CORE_ID, 0);
cc = (struct chipcregs *) ai_setcore(sih, CC_CORE_ID, 0);

val = R_REG(&cc->chipcontrol);

Expand All @@ -2205,13 +2209,13 @@ void ai_chipcontrl_epa4331(struct si_pub *sih, bool on)
void ai_epa_4313war(struct si_pub *sih)
{
struct si_info *sii;
chipcregs_t *cc;
struct chipcregs *cc;
uint origidx;

sii = SI_INFO(sih);
origidx = ai_coreidx(sih);

cc = (chipcregs_t *) ai_setcore(sih, CC_CORE_ID, 0);
cc = (struct chipcregs *) ai_setcore(sih, CC_CORE_ID, 0);

/* EPA Fix */
W_REG(&cc->gpiocontrol,
Expand Down Expand Up @@ -2243,7 +2247,7 @@ bool ai_is_sprom_available(struct si_pub *sih)
if (sih->ccrev >= 31) {
struct si_info *sii;
uint origidx;
chipcregs_t *cc;
struct chipcregs *cc;
u32 sromctrl;

if ((sih->cccaps & CC_CAP_SROM) == 0)
Expand Down
24 changes: 12 additions & 12 deletions drivers/staging/brcm80211/brcmsmac/d11.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -73,8 +73,8 @@ struct pio2regs {

/* a pair of pio channels(tx and rx) */
struct pio2regp {
pio2regs_t tx;
pio2regs_t rx;
struct pio2regs tx;
struct pio2regs rx;
};

/* 4byte-wide pio register set per channel(xmt or rcv) */
Expand All @@ -85,8 +85,8 @@ struct pio4regs {

/* a pair of pio channels(tx and rx) */
struct pio4regp {
pio4regs_t tx;
pio4regs_t rx;
struct pio4regs tx;
struct pio4regs rx;
};

/* read: 32-bit register that can be read as 32-bit or as 2 16-bit
Expand All @@ -101,10 +101,10 @@ union pmqreg {
};

struct fifo64 {
dma64regs_t dmaxmt; /* dma tx */
pio4regs_t piotx; /* pio tx */
dma64regs_t dmarcv; /* dma rx */
pio4regs_t piorx; /* pio rx */
struct dma64regs dmaxmt; /* dma tx */
struct pio4regs piotx; /* pio tx */
struct dma64regs dmarcv; /* dma rx */
struct pio4regs piorx; /* pio rx */
};

/*
Expand All @@ -120,7 +120,7 @@ struct d11regs {
u32 usectimer; /* 0x1c *//* for corerev >= 26 */

/* Interrupt Control *//* 0x20 */
intctrlregs_t intctrlregs[8];
struct intctrlregs intctrlregs[8];

u32 PAD[40]; /* 0x60 - 0xFC */

Expand All @@ -139,7 +139,7 @@ struct d11regs {
u32 PAD[2]; /* 0x138 - 0x13C */

/* PMQ registers */
pmqreg_t pmqreg; /* 0x140 */
union pmqreg pmqreg; /* 0x140 */
u32 pmqpatl; /* 0x144 */
u32 pmqpath; /* 0x148 */
u32 PAD; /* 0x14C */
Expand Down Expand Up @@ -179,10 +179,10 @@ struct d11regs {
u32 PAD[5]; /* 0x1ec - 0x1fc */

/* 0x200-0x37F dma/pio registers */
fifo64_t fifo64regs[6];
struct fifo64 fifo64regs[6];

/* FIFO diagnostic port access */
dma32diag_t dmafifo; /* 0x380 - 0x38C */
struct dma32diag dmafifo; /* 0x380 - 0x38C */

u32 aggfifocnt; /* 0x390 */
u32 aggfifodata; /* 0x394 */
Expand Down
16 changes: 9 additions & 7 deletions drivers/staging/brcm80211/brcmsmac/dma.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -240,8 +240,10 @@ struct dma_info {

union {
struct {
dma64regs_t *txregs_64; /* 64-bit dma tx engine registers */
dma64regs_t *rxregs_64; /* 64-bit dma rx engine registers */
/* 64-bit dma tx engine registers */
struct dma64regs *txregs_64;
/* 64-bit dma rx engine registers */
struct dma64regs *rxregs_64;
/* pointer to dma64 tx descriptor ring */
struct dma64desc *txd_64;
/* pointer to dma64 rx descriptor ring */
Expand Down Expand Up @@ -385,7 +387,7 @@ static void dma64_txreclaim(struct dma_info *di, enum txd_range range);
static bool dma64_txstopped(struct dma_info *di);
static bool dma64_rxstopped(struct dma_info *di);
static bool dma64_rxenabled(struct dma_info *di);
static bool _dma64_addrext(dma64regs_t *dma64regs);
static bool _dma64_addrext(struct dma64regs *dma64regs);

static inline u32 parity32(u32 data);

Expand Down Expand Up @@ -459,8 +461,8 @@ struct dma_pub *dma_attach(char *name, struct si_pub *sih,
di->dma64 = ((ai_core_sflags(sih, 0, 0) & SISF_DMA64) == SISF_DMA64);

/* init dma reg pointer */
di->d64txregs = (dma64regs_t *) dmaregstx;
di->d64rxregs = (dma64regs_t *) dmaregsrx;
di->d64txregs = (struct dma64regs *) dmaregstx;
di->d64rxregs = (struct dma64regs *) dmaregsrx;
di->dma.di_fn = (const struct di_fcn_s *)&dma64proc;

/* Default flags (which can be changed by the driver calling dma_ctrlflags
Expand Down Expand Up @@ -1683,7 +1685,7 @@ static void *dma64_getnexttxp(struct dma_info *di, enum txd_range range)
if (range == DMA_RANGE_ALL)
end = di->txout;
else {
dma64regs_t *dregs = di->d64txregs;
struct dma64regs *dregs = di->d64txregs;

end = (u16) (B2I(((R_REG(&dregs->status0) &
D64_XS0_CD_MASK) -
Expand Down Expand Up @@ -1795,7 +1797,7 @@ static void *dma64_getnextrxp(struct dma_info *di, bool forceall)
return rxp;
}

static bool _dma64_addrext(dma64regs_t *dma64regs)
static bool _dma64_addrext(struct dma64regs *dma64regs)
{
u32 w;
OR_REG(&dma64regs->control, D64_XC_AE);
Expand Down
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