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ARM: S5PV210: Add IRQ_EINT interrupt support.
Add support for external interrupts on S5PV210. Signed-off-by: Jongpill Lee <boyko.lee@samsung.com> Signed-off-by: Pannaga Bhushan <p.bhushan@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> [ben-linux@fluff.org: Ext => IRQ_EINT in title] Signed-off-by: Ben Dooks <ben-linux@fluff.org>
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May 20, 2010
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,44 @@ | ||
| /* linux/arch/arm/mach-s5pv210/include/mach/regs-gpio.h | ||
| * | ||
| * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
| * http://www.samsung.com | ||
| * | ||
| * S5PV210 - GPIO (including EINT) register definitions | ||
| * | ||
| * This program is free software; you can redistribute it and/or modify | ||
| * it under the terms of the GNU General Public License version 2 as | ||
| * published by the Free Software Foundation. | ||
| */ | ||
|
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| #ifndef __ASM_ARCH_REGS_GPIO_H | ||
| #define __ASM_ARCH_REGS_GPIO_H __FILE__ | ||
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| #include <mach/map.h> | ||
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| #define S5PV210_EINT30CON (S5P_VA_GPIO + 0xE00) | ||
| #define S5P_EINT_CON(x) (S5PV210_EINT30CON + ((x) * 0x4)) | ||
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| #define S5PV210_EINT30FLTCON0 (S5P_VA_GPIO + 0xE80) | ||
| #define S5P_EINT_FLTCON(x) (S5PV210_EINT30FLTCON0 + ((x) * 0x4)) | ||
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| #define S5PV210_EINT30MASK (S5P_VA_GPIO + 0xF00) | ||
| #define S5P_EINT_MASK(x) (S5PV210_EINT30MASK + ((x) * 0x4)) | ||
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| #define S5PV210_EINT30PEND (S5P_VA_GPIO + 0xF40) | ||
| #define S5P_EINT_PEND(x) (S5PV210_EINT30PEND + ((x) * 0x4)) | ||
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| #define eint_offset(irq) ((irq) < IRQ_EINT16_31 ? ((irq) - IRQ_EINT(0)) \ | ||
| : ((irq) - S5P_EINT_16_31_BASE)) | ||
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| #define EINT_REG_NR(x) (eint_offset(x) >> 3) | ||
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| #define eint_irq_to_bit(irq) (1 << (eint_offset(irq) & 0x7)) | ||
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| /* values for S5P_EXTINT0 */ | ||
| #define S5P_EXTINT_LOWLEV (0x00) | ||
| #define S5P_EXTINT_HILEV (0x01) | ||
| #define S5P_EXTINT_FALLEDGE (0x02) | ||
| #define S5P_EXTINT_RISEEDGE (0x03) | ||
| #define S5P_EXTINT_BOTHEDGE (0x04) | ||
|
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| #endif /* __ASM_ARCH_REGS_GPIO_H */ |
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,213 @@ | ||
| /* linux/arch/arm/plat-s5p/irq-eint.c | ||
| * | ||
| * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
| * http://www.samsung.com | ||
| * | ||
| * S5P - IRQ EINT support | ||
| * | ||
| * This program is free software; you can redistribute it and/or modify | ||
| * it under the terms of the GNU General Public License version 2 as | ||
| * published by the Free Software Foundation. | ||
| */ | ||
|
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| #include <linux/kernel.h> | ||
| #include <linux/interrupt.h> | ||
| #include <linux/irq.h> | ||
| #include <linux/io.h> | ||
| #include <linux/sysdev.h> | ||
| #include <linux/gpio.h> | ||
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| #include <asm/hardware/vic.h> | ||
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| #include <plat/regs-irqtype.h> | ||
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| #include <mach/map.h> | ||
| #include <plat/cpu.h> | ||
| #include <plat/pm.h> | ||
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| #include <plat/gpio-cfg.h> | ||
| #include <mach/regs-gpio.h> | ||
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| static inline void s5p_irq_eint_mask(unsigned int irq) | ||
| { | ||
| u32 mask; | ||
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| mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq))); | ||
| mask |= eint_irq_to_bit(irq); | ||
| __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq))); | ||
| } | ||
|
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| static void s5p_irq_eint_unmask(unsigned int irq) | ||
| { | ||
| u32 mask; | ||
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| mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq))); | ||
| mask &= ~(eint_irq_to_bit(irq)); | ||
| __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq))); | ||
| } | ||
|
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| static inline void s5p_irq_eint_ack(unsigned int irq) | ||
| { | ||
| __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq))); | ||
| } | ||
|
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| static void s5p_irq_eint_maskack(unsigned int irq) | ||
| { | ||
| /* compiler should in-line these */ | ||
| s5p_irq_eint_mask(irq); | ||
| s5p_irq_eint_ack(irq); | ||
| } | ||
|
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| static int s5p_irq_eint_set_type(unsigned int irq, unsigned int type) | ||
| { | ||
| int offs = eint_offset(irq); | ||
| int shift; | ||
| u32 ctrl, mask; | ||
| u32 newvalue = 0; | ||
|
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| switch (type) { | ||
| case IRQ_TYPE_EDGE_RISING: | ||
| newvalue = S5P_EXTINT_RISEEDGE; | ||
| break; | ||
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| case IRQ_TYPE_EDGE_FALLING: | ||
| newvalue = S5P_EXTINT_RISEEDGE; | ||
| break; | ||
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| case IRQ_TYPE_EDGE_BOTH: | ||
| newvalue = S5P_EXTINT_BOTHEDGE; | ||
| break; | ||
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| case IRQ_TYPE_LEVEL_LOW: | ||
| newvalue = S5P_EXTINT_LOWLEV; | ||
| break; | ||
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| case IRQ_TYPE_LEVEL_HIGH: | ||
| newvalue = S5P_EXTINT_HILEV; | ||
| break; | ||
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| default: | ||
| printk(KERN_ERR "No such irq type %d", type); | ||
| return -EINVAL; | ||
| } | ||
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| shift = (offs & 0x7) * 4; | ||
| mask = 0x7 << shift; | ||
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| ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(irq))); | ||
| ctrl &= ~mask; | ||
| ctrl |= newvalue << shift; | ||
| __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(irq))); | ||
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| if ((0 <= offs) && (offs < 8)) | ||
| s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE); | ||
|
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| else if ((8 <= offs) && (offs < 16)) | ||
| s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE); | ||
|
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| else if ((16 <= offs) && (offs < 24)) | ||
| s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE); | ||
|
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| else if ((24 <= offs) && (offs < 32)) | ||
| s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE); | ||
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| else | ||
| printk(KERN_ERR "No such irq number %d", offs); | ||
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| return 0; | ||
| } | ||
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| static struct irq_chip s5p_irq_eint = { | ||
| .name = "s5p-eint", | ||
| .mask = s5p_irq_eint_mask, | ||
| .unmask = s5p_irq_eint_unmask, | ||
| .mask_ack = s5p_irq_eint_maskack, | ||
| .ack = s5p_irq_eint_ack, | ||
| .set_type = s5p_irq_eint_set_type, | ||
| #ifdef CONFIG_PM | ||
| .set_wake = s3c_irqext_wake, | ||
| #endif | ||
| }; | ||
|
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| /* s5p_irq_demux_eint | ||
| * | ||
| * This function demuxes the IRQ from the group0 external interrupts, | ||
| * from EINTs 16 to 31. It is designed to be inlined into the specific | ||
| * handler s5p_irq_demux_eintX_Y. | ||
| * | ||
| * Each EINT pend/mask registers handle eight of them. | ||
| */ | ||
| static inline void s5p_irq_demux_eint(unsigned int start) | ||
| { | ||
| u32 status; | ||
| u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start))); | ||
| unsigned int irq; | ||
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| status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start))); | ||
| status &= ~mask; | ||
| status &= 0xff; | ||
|
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| while (status) { | ||
| irq = fls(status); | ||
| generic_handle_irq(irq - 1 + start); | ||
| status &= ~(1 << irq); | ||
| } | ||
| } | ||
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| static void s5p_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) | ||
| { | ||
| s5p_irq_demux_eint(IRQ_EINT(16)); | ||
| s5p_irq_demux_eint(IRQ_EINT(24)); | ||
| } | ||
|
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| static inline void s5p_irq_vic_eint_mask(unsigned int irq) | ||
| { | ||
| s5p_irq_eint_mask(irq); | ||
| } | ||
|
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| static void s5p_irq_vic_eint_unmask(unsigned int irq) | ||
| { | ||
| s5p_irq_eint_unmask(irq); | ||
| } | ||
|
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| static inline void s5p_irq_vic_eint_ack(unsigned int irq) | ||
| { | ||
| __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq))); | ||
| } | ||
|
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| static void s5p_irq_vic_eint_maskack(unsigned int irq) | ||
| { | ||
| s5p_irq_vic_eint_mask(irq); | ||
| s5p_irq_vic_eint_ack(irq); | ||
| } | ||
|
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| static struct irq_chip s5p_irq_vic_eint = { | ||
| .name = "s5p_vic_eint", | ||
| .mask = s5p_irq_vic_eint_mask, | ||
| .unmask = s5p_irq_vic_eint_unmask, | ||
| .mask_ack = s5p_irq_vic_eint_maskack, | ||
| .ack = s5p_irq_vic_eint_ack, | ||
| .set_type = s5p_irq_eint_set_type, | ||
| #ifdef CONFIG_PM | ||
| .set_wake = s3c_irqext_wake, | ||
| #endif | ||
| }; | ||
|
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| int __init s5p_init_irq_eint(void) | ||
| { | ||
| int irq; | ||
|
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| for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++) | ||
| set_irq_chip(irq, &s5p_irq_vic_eint); | ||
|
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| for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) { | ||
| set_irq_chip(irq, &s5p_irq_eint); | ||
| set_irq_handler(irq, handle_level_irq); | ||
| set_irq_flags(irq, IRQF_VALID); | ||
| } | ||
|
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| set_irq_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31); | ||
| return 0; | ||
| } | ||
|
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| arch_initcall(s5p_init_irq_eint); |