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yaml
---
r: 187350
b: refs/heads/master
c: 35accd2
h: refs/heads/master
v: v3
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Ben Dooks committed Jan 15, 2010
1 parent a24d9fb commit 0e262ac
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Showing 2 changed files with 7 additions and 114 deletions.
2 changes: 1 addition & 1 deletion [refs]
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---
refs/heads/master: 37872bb9efddf9518cc77c43f9fa8fc6bfd3d727
refs/heads/master: 35accd2f6639a9245488f2f389e3c6372c7641e4
119 changes: 6 additions & 113 deletions trunk/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
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Expand Up @@ -61,73 +61,10 @@
#define S5PC100_EPLL_MASK 0xffffffff
#define S5PC100_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s)))

/* CLKSRC0 */
#define S5PC100_CLKSRC0_APLL_MASK (0x1<<0)
#define S5PC100_CLKSRC0_APLL_SHIFT (0)
#define S5PC100_CLKSRC0_MPLL_MASK (0x1<<4)
#define S5PC100_CLKSRC0_MPLL_SHIFT (4)
#define S5PC100_CLKSRC0_EPLL_MASK (0x1<<8)
#define S5PC100_CLKSRC0_EPLL_SHIFT (8)
#define S5PC100_CLKSRC0_HPLL_MASK (0x1<<12)
#define S5PC100_CLKSRC0_HPLL_SHIFT (12)
#define S5PC100_CLKSRC0_AMMUX_MASK (0x1<<16)
#define S5PC100_CLKSRC0_AMMUX_SHIFT (16)
#define S5PC100_CLKSRC0_HREF_MASK (0x1<<20)
#define S5PC100_CLKSRC0_HREF_SHIFT (20)
#define S5PC100_CLKSRC0_ONENAND_MASK (0x1<<24)
#define S5PC100_CLKSRC0_ONENAND_SHIFT (24)


/* CLKSRC1 */
#define S5PC100_CLKSRC1_UART_MASK (0x1<<0)
#define S5PC100_CLKSRC1_UART_SHIFT (0)
#define S5PC100_CLKSRC1_SPI0_MASK (0x3<<4)
#define S5PC100_CLKSRC1_SPI0_SHIFT (4)
#define S5PC100_CLKSRC1_SPI1_MASK (0x3<<8)
#define S5PC100_CLKSRC1_SPI1_SHIFT (8)
#define S5PC100_CLKSRC1_SPI2_MASK (0x3<<12)
#define S5PC100_CLKSRC1_SPI2_SHIFT (12)
#define S5PC100_CLKSRC1_IRDA_MASK (0x3<<16)
#define S5PC100_CLKSRC1_IRDA_SHIFT (16)
#define S5PC100_CLKSRC1_UHOST_MASK (0x3<<20)
#define S5PC100_CLKSRC1_UHOST_SHIFT (20)
#define S5PC100_CLKSRC1_CLK48M_MASK (0x1<<24)
/* CLKSRC0..CLKSRC3 -> mostly removed due to clksrc updates */
#define S5PC100_CLKSRC1_CLK48M_MASK (0x1<<24)
#define S5PC100_CLKSRC1_CLK48M_SHIFT (24)

/* CLKSRC2 */
#define S5PC100_CLKSRC2_MMC0_MASK (0x3<<0)
#define S5PC100_CLKSRC2_MMC0_SHIFT (0)
#define S5PC100_CLKSRC2_MMC1_MASK (0x3<<4)
#define S5PC100_CLKSRC2_MMC1_SHIFT (4)
#define S5PC100_CLKSRC2_MMC2_MASK (0x3<<8)
#define S5PC100_CLKSRC2_MMC2_SHIFT (8)
#define S5PC100_CLKSRC2_LCD_MASK (0x3<<12)
#define S5PC100_CLKSRC2_LCD_SHIFT (12)
#define S5PC100_CLKSRC2_FIMC0_MASK (0x3<<16)
#define S5PC100_CLKSRC2_FIMC0_SHIFT (16)
#define S5PC100_CLKSRC2_FIMC1_MASK (0x3<<20)
#define S5PC100_CLKSRC2_FIMC1_SHIFT (20)
#define S5PC100_CLKSRC2_FIMC2_MASK (0x3<<24)
#define S5PC100_CLKSRC2_FIMC2_SHIFT (24)
#define S5PC100_CLKSRC2_MIXER_MASK (0x3<<28)
#define S5PC100_CLKSRC2_MIXER_SHIFT (28)

/* CLKSRC3 */
#define S5PC100_CLKSRC3_PWI_MASK (0x3<<0)
#define S5PC100_CLKSRC3_PWI_SHIFT (0)
#define S5PC100_CLKSRC3_HCLKD2_MASK (0x1<<4)
#define S5PC100_CLKSRC3_HCLKD2_SHIFT (4)
#define S5PC100_CLKSRC3_I2SD2_MASK (0x3<<8)
#define S5PC100_CLKSRC3_I2SD2_SHIFT (8)
#define S5PC100_CLKSRC3_AUDIO0_MASK (0x7<<12)
#define S5PC100_CLKSRC3_AUDIO0_SHIFT (12)
#define S5PC100_CLKSRC3_AUDIO1_MASK (0x7<<16)
#define S5PC100_CLKSRC3_AUDIO1_SHIFT (16)
#define S5PC100_CLKSRC3_AUDIO2_MASK (0x7<<20)
#define S5PC100_CLKSRC3_AUDIO2_SHIFT (20)
#define S5PC100_CLKSRC3_SPDIF_MASK (0x3<<24)
#define S5PC100_CLKSRC3_SPDIF_SHIFT (24)

/* CLKDIV0 */
#define S5PC100_CLKDIV0_APLL_MASK (0x1<<0)
#define S5PC100_CLKDIV0_APLL_SHIFT (0)
Expand All @@ -140,7 +77,7 @@
#define S5PC100_CLKDIV0_SECSS_MASK (0x7<<16)
#define S5PC100_CLKDIV0_SECSS_SHIFT (16)

/* CLKDIV1 */
/* CLKDIV1 (OneNAND clock only used in one place, removed) */
#define S5PC100_CLKDIV1_APLL2_MASK (0x7<<0)
#define S5PC100_CLKDIV1_APLL2_SHIFT (0)
#define S5PC100_CLKDIV1_MPLL_MASK (0x3<<4)
Expand All @@ -151,56 +88,12 @@
#define S5PC100_CLKDIV1_D1_SHIFT (12)
#define S5PC100_CLKDIV1_PCLKD1_MASK (0x7<<16)
#define S5PC100_CLKDIV1_PCLKD1_SHIFT (16)
#define S5PC100_CLKDIV1_ONENAND_MASK (0x3<<20)
#define S5PC100_CLKDIV1_ONENAND_SHIFT (20)
#define S5PC100_CLKDIV1_CAM_MASK (0x1F<<24)
#define S5PC100_CLKDIV1_CAM_SHIFT (24)

/* CLKDIV2 */
#define S5PC100_CLKDIV2_UART_MASK (0x7<<0)
#define S5PC100_CLKDIV2_UART_SHIFT (0)
#define S5PC100_CLKDIV2_SPI0_MASK (0xf<<4)
#define S5PC100_CLKDIV2_SPI0_SHIFT (4)
#define S5PC100_CLKDIV2_SPI1_MASK (0xf<<8)
#define S5PC100_CLKDIV2_SPI1_SHIFT (8)
#define S5PC100_CLKDIV2_SPI2_MASK (0xf<<12)
#define S5PC100_CLKDIV2_SPI2_SHIFT (12)
#define S5PC100_CLKDIV2_IRDA_MASK (0xf<<16)
#define S5PC100_CLKDIV2_IRDA_SHIFT (16)
#define S5PC100_CLKDIV2_UHOST_MASK (0xf<<20)
#define S5PC100_CLKDIV2_UHOST_SHIFT (20)

/* CLKDIV3 */
#define S5PC100_CLKDIV3_MMC0_MASK (0xf<<0)
#define S5PC100_CLKDIV3_MMC0_SHIFT (0)
#define S5PC100_CLKDIV3_MMC1_MASK (0xf<<4)
#define S5PC100_CLKDIV3_MMC1_SHIFT (4)
#define S5PC100_CLKDIV3_MMC2_MASK (0xf<<8)
#define S5PC100_CLKDIV3_MMC2_SHIFT (8)
#define S5PC100_CLKDIV3_LCD_MASK (0xf<<12)
#define S5PC100_CLKDIV3_LCD_SHIFT (12)
#define S5PC100_CLKDIV3_FIMC0_MASK (0xf<<16)
#define S5PC100_CLKDIV3_FIMC0_SHIFT (16)
#define S5PC100_CLKDIV3_FIMC1_MASK (0xf<<20)
#define S5PC100_CLKDIV3_FIMC1_SHIFT (20)
#define S5PC100_CLKDIV3_FIMC2_MASK (0xf<<24)
#define S5PC100_CLKDIV3_FIMC2_SHIFT (24)
#define S5PC100_CLKDIV3_HDMI_MASK (0xf<<28)
#define S5PC100_CLKDIV3_HDMI_SHIFT (28)

/* CLKDIV4 */
#define S5PC100_CLKDIV4_PWI_MASK (0x7<<0)
#define S5PC100_CLKDIV4_PWI_SHIFT (0)
#define S5PC100_CLKDIV4_HCLKD2_MASK (0x7<<4)
#define S5PC100_CLKDIV4_HCLKD2_SHIFT (4)
#define S5PC100_CLKDIV4_I2SD2_MASK (0xf<<8)
#define S5PC100_CLKDIV4_I2SD2_SHIFT (8)
#define S5PC100_CLKDIV4_AUDIO0_MASK (0xf<<12)
#define S5PC100_CLKDIV4_AUDIO0_SHIFT (12)
#define S5PC100_CLKDIV4_AUDIO1_MASK (0xf<<16)
#define S5PC100_CLKDIV4_AUDIO1_SHIFT (16)
#define S5PC100_CLKDIV4_AUDIO2_MASK (0xf<<20)
#define S5PC100_CLKDIV4_AUDIO2_SHIFT (20)
/* CLKDIV2 => removed in clksrc update */
/* CLKDIV3 => removed in clksrc update, or not needed */
/* CLKDIV4 => removed in clksrc update, or not needed */

/* HCLKD0/PCLKD0 Clock Gate 0 Registers */
#define S5PC100_CLKGATE_D00_INTC (1<<0)
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