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yaml
---
r: 357903
b: refs/heads/master
c: 1ce1703
h: refs/heads/master
i:
  357901: 94c7e8f
  357899: 66ea156
  357895: 2feb939
  357887: 39060d6
v: v3
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Daniel Vetter committed Dec 6, 2012
1 parent 5cc52cc commit 0fc44dd
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Showing 2 changed files with 6 additions and 17 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: ea9b6006b51b79cfbb87c1ca81923761b7799c0f
refs/heads/master: 1ce17038093f02e708e5816f645bbec63aff8bd2
21 changes: 5 additions & 16 deletions trunk/drivers/gpu/drm/i915/intel_dp.c
Original file line number Diff line number Diff line change
Expand Up @@ -910,26 +910,15 @@ static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
dpa_ctl &= ~DP_PLL_FREQ_MASK;

if (clock < 200000) {
u32 temp;
/* For a long time we've carried around a ILK-DevA w/a for the
* 160MHz clock. If we're really unlucky, it's still required.
*/
DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
dpa_ctl |= DP_PLL_FREQ_160MHZ;
/* workaround for 160Mhz:
1) program 0x4600c bits 15:0 = 0x8124
2) program 0x46010 bit 0 = 1
3) program 0x46034 bit 24 = 1
4) program 0x64000 bit 14 = 1
*/
temp = I915_READ(0x4600c);
temp &= 0xffff0000;
I915_WRITE(0x4600c, temp | 0x8124);

temp = I915_READ(0x46010);
I915_WRITE(0x46010, temp | 1);

temp = I915_READ(0x46034);
I915_WRITE(0x46034, temp | (1 << 24));
} else {
dpa_ctl |= DP_PLL_FREQ_270MHZ;
}

I915_WRITE(DP_A, dpa_ctl);

POSTING_READ(DP_A);
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