---

yaml --- r: 311679 b: refs/heads/master c: c520c92 h: refs/heads/master i: 311677: dd7d2eb 311675: 27c4bbc 311671: a4828a6 311663: 1d6c950 311647: 5fd51f3 311615: bb74b3c 311551: 606cd78 v: v3
git-mirror · Jul 4, 2012 · 1028bf8 · 1028bf8
1 parent d7bbe68
commit 1028bf8
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Showing 2 changed files with 9 additions and 2 deletions.
diff --git a/[refs] b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 396c89b327269c5a90bdd6152b5339e4cd2b8e73
+refs/heads/master: c520c921eacdced7e2095ba6cbbb9921906c7b67
diff --git a/trunk/arch/arm/mach-imx/clk-imx35.c b/trunk/arch/arm/mach-imx/clk-imx35.c
@@ -201,7 +201,6 @@ int __init mx35_clocks_init()
 			pr_err("i.MX35 clk %d: register failed with %ld\n",
 				i, PTR_ERR(clk[i]));
 
-
 	clk_register_clkdev(clk[pata_gate], NULL, "pata_imx");
 	clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0");
 	clk_register_clkdev(clk[can2_gate], NULL, "flexcan.1");
@@ -264,6 +263,14 @@ int __init mx35_clocks_init()
 	clk_prepare_enable(clk[iim_gate]);
 	clk_prepare_enable(clk[emi_gate]);
 
+	/*
+	 * SCC is needed to boot via mmc after a watchdog reset. The clock code
+	 * before conversion to common clk also enabled UART1 (which isn't
+	 * handled here and not needed for mmc) and IIM (which is enabled
+	 * unconditionally above).
+	 */
+	clk_prepare_enable(clk[scc_gate]);
+
 	imx_print_silicon_rev("i.MX35", mx35_revision());
 
 #ifdef CONFIG_MXC_USE_EPIT