---

yaml
---
r: 200028
b: refs/heads/master
c: ba6c5c6
h: refs/heads/master
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 67166af4abc11d9c0deb497ebe0b562f69c71942
+refs/heads/master: ba6c5c62eeb877da638e43f1282f778432142eec

trunk/drivers/edac/i7core_edac.c

@@ -409,12 +409,12 @@ static int i7core_get_active_channels(u8 socket, unsigned *channels,
 	return 0;
 }
 
-static int get_dimm_config(struct mem_ctl_info *mci, u8 socket)
+static int get_dimm_config(struct mem_ctl_info *mci, int *csrow, u8 socket)
 {
 	struct i7core_pvt *pvt = mci->pvt_info;
 	struct csrow_info *csr;
 	struct pci_dev *pdev;
-	int i, j, csrow = 0;
+	int i, j;
 	unsigned long last_page = 0;
 	enum edac_type mode;
 	enum mem_type mtype;
@@ -534,15 +534,15 @@ static int get_dimm_config(struct mem_ctl_info *mci, u8 socket)
 			npages = size << (20 - PAGE_SHIFT);
 #endif
 
-			csr = &mci->csrows[csrow];
+			csr = &mci->csrows[*csrow];
 			csr->first_page = last_page + 1;
 			last_page += npages;
 			csr->last_page = last_page;
 			csr->nr_pages = npages;
 
 			csr->page_mask = 0;
 			csr->grain = 8;
-			csr->csrow_idx = csrow;
+			csr->csrow_idx = *csrow;
 			csr->nr_channels = 1;
 
 			csr->channels[0].chan_idx = i;
@@ -565,7 +565,7 @@ static int get_dimm_config(struct mem_ctl_info *mci, u8 socket)
 			csr->edac_mode = mode;
 			csr->mtype = mtype;
 
-			csrow++;
+			(*csrow)++;
 		}
 
 		pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
@@ -1424,6 +1424,7 @@ static int __devinit i7core_probe(struct pci_dev *pdev,
 	struct i7core_pvt *pvt;
 	int num_channels = 0;
 	int num_csrows = 0;
+	int csrow = 0;
 	int dev_idx = id->driver_data;
 	int rc, i;
 	u8 sockets;
@@ -1495,7 +1496,7 @@ static int __devinit i7core_probe(struct pci_dev *pdev,
 
 	/* Get dimm basic config */
 	for (i = 0; i < sockets; i++)
-		get_dimm_config(mci, i);
+		get_dimm_config(mci, &csrow, i);
 
 	/* add this new MC control structure to EDAC's list of MCs */
 	if (unlikely(edac_mc_add_mc(mci))) {