---

yaml
---
r: 62474
b: refs/heads/master
c: f51c945
h: refs/heads/master
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: abd4f7505bafdd6c5319fe3cb5caf9af6104e17a
+refs/heads/master: f51c94528a9bc73504928926ca4d791a2b7ddd7c

trunk/arch/x86_64/kernel/process.c

@@ -342,10 +342,10 @@ void __show_regs(struct pt_regs * regs)
 	rdmsrl(MSR_GS_BASE, gs); 
 	rdmsrl(MSR_KERNEL_GS_BASE, shadowgs); 
 
-	asm("movq %%cr0, %0": "=r" (cr0));
-	asm("movq %%cr2, %0": "=r" (cr2));
-	asm("movq %%cr3, %0": "=r" (cr3));
-	asm("movq %%cr4, %0": "=r" (cr4));
+	cr0 = read_cr0();
+	cr2 = read_cr2();
+	cr3 = read_cr3();
+	cr4 = read_cr4();
 
 	printk("FS:  %016lx(%04x) GS:%016lx(%04x) knlGS:%016lx\n", 
 	       fs,fsindex,gs,gsindex,shadowgs); 

trunk/arch/x86_64/kernel/suspend.c

@@ -55,11 +55,11 @@ void __save_processor_state(struct saved_context *ctxt)
 	 * control registers 
 	 */
 	rdmsrl(MSR_EFER, ctxt->efer);
-	asm volatile ("movq %%cr0, %0" : "=r" (ctxt->cr0));
-	asm volatile ("movq %%cr2, %0" : "=r" (ctxt->cr2));
-	asm volatile ("movq %%cr3, %0" : "=r" (ctxt->cr3));
-	asm volatile ("movq %%cr4, %0" : "=r" (ctxt->cr4));
-	asm volatile ("movq %%cr8, %0" : "=r" (ctxt->cr8));
+	ctxt->cr0 = read_cr0();
+	ctxt->cr2 = read_cr2();
+	ctxt->cr3 = read_cr3();
+	ctxt->cr4 = read_cr4();
+	ctxt->cr8 = read_cr8();
 }
 
 void save_processor_state(void)
@@ -81,11 +81,11 @@ void __restore_processor_state(struct saved_context *ctxt)
 	 * control registers
 	 */
 	wrmsrl(MSR_EFER, ctxt->efer);
-	asm volatile ("movq %0, %%cr8" :: "r" (ctxt->cr8));
-	asm volatile ("movq %0, %%cr4" :: "r" (ctxt->cr4));
-	asm volatile ("movq %0, %%cr3" :: "r" (ctxt->cr3));
-	asm volatile ("movq %0, %%cr2" :: "r" (ctxt->cr2));
-	asm volatile ("movq %0, %%cr0" :: "r" (ctxt->cr0));
+	write_cr8(ctxt->cr8);
+	write_cr4(ctxt->cr4);
+	write_cr3(ctxt->cr3);
+	write_cr2(ctxt->cr2);
+	write_cr0(ctxt->cr0);
 
 	/*
 	 * now restore the descriptor tables to their proper values

trunk/arch/x86_64/mm/fault.c

@@ -159,7 +159,7 @@ void dump_pagetable(unsigned long address)
 	pmd_t *pmd;
 	pte_t *pte;
 
-	asm("movq %%cr3,%0" : "=r" (pgd));
+	pgd = (pgd_t *)read_cr3();
 
 	pgd = __va((unsigned long)pgd & PHYSICAL_PAGE_MASK); 
 	pgd += pgd_index(address);
@@ -316,7 +316,7 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs,
 	prefetchw(&mm->mmap_sem);
 
 	/* get the address */
-	__asm__("movq %%cr2,%0":"=r" (address));
+	address = read_cr2();
 
 	info.si_code = SEGV_MAPERR;
 

trunk/arch/x86_64/mm/init.c

@@ -383,7 +383,7 @@ void __meminit init_memory_mapping(unsigned long start, unsigned long end)
 	} 
 
 	if (!after_bootmem)
-		asm volatile("movq %%cr4,%0" : "=r" (mmu_cr4_features));
+		mmu_cr4_features = read_cr4();
 	__flush_tlb_all();
 }
 

trunk/include/asm-x86_64/system.h

@@ -75,19 +75,31 @@ static inline unsigned long read_cr0(void)
 	unsigned long cr0;
 	asm volatile("movq %%cr0,%0" : "=r" (cr0));
 	return cr0;
-} 
+}
 
 static inline void write_cr0(unsigned long val) 
 { 
 	asm volatile("movq %0,%%cr0" :: "r" (val));
-} 
+}
+
+static inline unsigned long read_cr2(void)
+{
+	unsigned long cr2;
+	asm("movq %%cr2,%0" : "=r" (cr2));
+	return cr2;
+}
+
+static inline void write_cr2(unsigned long val)
+{
+	asm volatile("movq %0,%%cr2" :: "r" (val));
+}
 
 static inline unsigned long read_cr3(void)
 { 
 	unsigned long cr3;
 	asm("movq %%cr3,%0" : "=r" (cr3));
 	return cr3;
-} 
+}
 
 static inline void write_cr3(unsigned long val)
 {
@@ -99,12 +111,24 @@ static inline unsigned long read_cr4(void)
 	unsigned long cr4;
 	asm("movq %%cr4,%0" : "=r" (cr4));
 	return cr4;
-} 
+}
 
 static inline void write_cr4(unsigned long val)
 { 
 	asm volatile("movq %0,%%cr4" :: "r" (val) : "memory");
-} 
+}
+
+static inline unsigned long read_cr8(void)
+{
+	unsigned long cr8;
+	asm("movq %%cr8,%0" : "=r" (cr8));
+	return cr8;
+}
+
+static inline void write_cr8(unsigned long val)
+{
+	asm volatile("movq %0,%%cr8" :: "r" (val) : "memory");
+}
 
 #define stts() write_cr0(8 | read_cr0())