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yaml
---
r: 36562
b: refs/heads/master
c: 6a39dd6
h: refs/heads/master
v: v3
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Daniel Jacobowitz authored and Russell King committed Sep 20, 2006
1 parent 09a0760 commit 112fdc5
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Showing 6 changed files with 63 additions and 60 deletions.
2 changes: 1 addition & 1 deletion [refs]
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Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 681a4991f83742a0d2325afbf7b7f22045ad5b30
refs/heads/master: 6a39dd6222dda5ee2414a1b42e8e62118742a49e
2 changes: 1 addition & 1 deletion trunk/arch/arm/kernel/traps.c
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Original file line number Diff line number Diff line change
Expand Up @@ -191,7 +191,7 @@ void show_stack(struct task_struct *tsk, unsigned long *sp)
if (tsk != current)
fp = thread_saved_fp(tsk);
else
asm("mov%? %0, fp" : "=r" (fp));
asm("mov %0, fp" : "=r" (fp) : : "cc");

c_backtrace(fp, 0x10);
barrier();
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27 changes: 15 additions & 12 deletions trunk/arch/arm/mach-footbridge/dc21285.c
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Original file line number Diff line number Diff line change
Expand Up @@ -69,16 +69,16 @@ dc21285_read_config(struct pci_bus *bus, unsigned int devfn, int where,
if (addr)
switch (size) {
case 1:
asm("ldr%?b %0, [%1, %2]"
: "=r" (v) : "r" (addr), "r" (where));
asm("ldrb %0, [%1, %2]"
: "=r" (v) : "r" (addr), "r" (where) : "cc");
break;
case 2:
asm("ldr%?h %0, [%1, %2]"
: "=r" (v) : "r" (addr), "r" (where));
asm("ldrh %0, [%1, %2]"
: "=r" (v) : "r" (addr), "r" (where) : "cc");
break;
case 4:
asm("ldr%? %0, [%1, %2]"
: "=r" (v) : "r" (addr), "r" (where));
asm("ldr %0, [%1, %2]"
: "=r" (v) : "r" (addr), "r" (where) : "cc");
break;
}

Expand All @@ -103,16 +103,19 @@ dc21285_write_config(struct pci_bus *bus, unsigned int devfn, int where,
if (addr)
switch (size) {
case 1:
asm("str%?b %0, [%1, %2]"
: : "r" (value), "r" (addr), "r" (where));
asm("strb %0, [%1, %2]"
: : "r" (value), "r" (addr), "r" (where)
: "cc");
break;
case 2:
asm("str%?h %0, [%1, %2]"
: : "r" (value), "r" (addr), "r" (where));
asm("strh %0, [%1, %2]"
: : "r" (value), "r" (addr), "r" (where)
: "cc");
break;
case 4:
asm("str%? %0, [%1, %2]"
: : "r" (value), "r" (addr), "r" (where));
asm("str %0, [%1, %2]"
: : "r" (value), "r" (addr), "r" (where)
: "cc");
break;
}

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8 changes: 4 additions & 4 deletions trunk/arch/arm/vfp/vfpinstr.h
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Original file line number Diff line number Diff line change
Expand Up @@ -73,14 +73,14 @@

#define fmrx(_vfp_) ({ \
u32 __v; \
asm("mrc%? p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmrx %0, " #_vfp_ \
: "=r" (__v)); \
asm("mrc p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmrx %0, " #_vfp_ \
: "=r" (__v) : : "cc"); \
__v; \
})

#define fmxr(_vfp_,_var_) \
asm("mcr%? p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr " #_vfp_ ", %0" \
: : "r" (_var_))
asm("mcr p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr " #_vfp_ ", %0" \
: : "r" (_var_) : "cc")

u32 vfp_single_cpdo(u32 inst, u32 fpscr);
u32 vfp_single_cprt(u32 inst, u32 fpscr, struct pt_regs *regs);
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8 changes: 4 additions & 4 deletions trunk/include/asm-arm/arch-l7200/io.h
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Original file line number Diff line number Diff line change
Expand Up @@ -31,9 +31,9 @@
static inline unsigned int __arch_getw(unsigned long a)
{
unsigned int value;
__asm__ __volatile__("ldr%?h %0, [%1, #0] @ getw"
__asm__ __volatile__("ldrh %0, [%1, #0] @ getw"
: "=&r" (value)
: "r" (a));
: "r" (a) : "cc");
return value;
}

Expand All @@ -42,8 +42,8 @@ static inline unsigned int __arch_getw(unsigned long a)

static inline void __arch_putw(unsigned int value, unsigned long a)
{
__asm__ __volatile__("str%?h %0, [%1, #0] @ putw"
: : "r" (value), "r" (a));
__asm__ __volatile__("strh %0, [%1, #0] @ putw"
: : "r" (value), "r" (a) : "cc");
}

/*
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76 changes: 38 additions & 38 deletions trunk/include/asm-arm/tlbflush.h
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Original file line number Diff line number Diff line change
Expand Up @@ -247,16 +247,16 @@ static inline void local_flush_tlb_all(void)
const unsigned int __tlb_flag = __cpu_tlb_flags;

if (tlb_flag(TLB_WB))
asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc");

if (tlb_flag(TLB_V3_FULL))
asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (zero));
asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
if (tlb_flag(TLB_V4_U_FULL | TLB_V6_U_FULL))
asm("mcr%? p15, 0, %0, c8, c7, 0" : : "r" (zero));
asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
if (tlb_flag(TLB_V4_D_FULL | TLB_V6_D_FULL))
asm("mcr%? p15, 0, %0, c8, c6, 0" : : "r" (zero));
asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL))
asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
}

static inline void local_flush_tlb_mm(struct mm_struct *mm)
Expand All @@ -266,25 +266,25 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
const unsigned int __tlb_flag = __cpu_tlb_flags;

if (tlb_flag(TLB_WB))
asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc");

if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) {
if (tlb_flag(TLB_V3_FULL))
asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (zero));
asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
if (tlb_flag(TLB_V4_U_FULL))
asm("mcr%? p15, 0, %0, c8, c7, 0" : : "r" (zero));
asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
if (tlb_flag(TLB_V4_D_FULL))
asm("mcr%? p15, 0, %0, c8, c6, 0" : : "r" (zero));
asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
if (tlb_flag(TLB_V4_I_FULL))
asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
}

if (tlb_flag(TLB_V6_U_ASID))
asm("mcr%? p15, 0, %0, c8, c7, 2" : : "r" (asid));
asm("mcr p15, 0, %0, c8, c7, 2" : : "r" (asid) : "cc");
if (tlb_flag(TLB_V6_D_ASID))
asm("mcr%? p15, 0, %0, c8, c6, 2" : : "r" (asid));
asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc");
if (tlb_flag(TLB_V6_I_ASID))
asm("mcr%? p15, 0, %0, c8, c5, 2" : : "r" (asid));
asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
}

static inline void
Expand All @@ -296,27 +296,27 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);

if (tlb_flag(TLB_WB))
asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero));

if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
if (tlb_flag(TLB_V3_PAGE))
asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (uaddr));
asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (uaddr) : "cc");
if (tlb_flag(TLB_V4_U_PAGE))
asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (uaddr));
asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
if (tlb_flag(TLB_V4_D_PAGE))
asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (uaddr));
asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
if (tlb_flag(TLB_V4_I_PAGE))
asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (uaddr));
asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
}

if (tlb_flag(TLB_V6_U_PAGE))
asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (uaddr));
asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
if (tlb_flag(TLB_V6_D_PAGE))
asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (uaddr));
asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
if (tlb_flag(TLB_V6_I_PAGE))
asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (uaddr));
asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
}

static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
Expand All @@ -327,31 +327,31 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
kaddr &= PAGE_MASK;

if (tlb_flag(TLB_WB))
asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc");

if (tlb_flag(TLB_V3_PAGE))
asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (kaddr));
asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (kaddr) : "cc");
if (tlb_flag(TLB_V4_U_PAGE))
asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (kaddr));
asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
if (tlb_flag(TLB_V4_D_PAGE))
asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (kaddr));
asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
if (tlb_flag(TLB_V4_I_PAGE))
asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (kaddr));
asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");

if (tlb_flag(TLB_V6_U_PAGE))
asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (kaddr));
asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
if (tlb_flag(TLB_V6_D_PAGE))
asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (kaddr));
asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
if (tlb_flag(TLB_V6_I_PAGE))
asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (kaddr));
asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");

/* The ARM ARM states that the completion of a TLB maintenance
* operation is only guaranteed by a DSB instruction
*/
if (tlb_flag(TLB_V6_U_PAGE | TLB_V6_D_PAGE | TLB_V6_I_PAGE))
asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc");
}

/*
Expand All @@ -373,20 +373,20 @@ static inline void flush_pmd_entry(pmd_t *pmd)
const unsigned int __tlb_flag = __cpu_tlb_flags;

if (tlb_flag(TLB_DCLEAN))
asm("mcr%? p15, 0, %0, c7, c10, 1 @ flush_pmd"
: : "r" (pmd));
asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd"
: : "r" (pmd) : "cc");
if (tlb_flag(TLB_WB))
asm("mcr%? p15, 0, %0, c7, c10, 4 @ flush_pmd"
: : "r" (zero));
asm("mcr p15, 0, %0, c7, c10, 4 @ flush_pmd"
: : "r" (zero) : "cc");
}

static inline void clean_pmd_entry(pmd_t *pmd)
{
const unsigned int __tlb_flag = __cpu_tlb_flags;

if (tlb_flag(TLB_DCLEAN))
asm("mcr%? p15, 0, %0, c7, c10, 1 @ flush_pmd"
: : "r" (pmd));
asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd"
: : "r" (pmd) : "cc");
}

#undef tlb_flag
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