---

yaml --- r: 191159 b: refs/heads/master c: 40b91cd h: refs/heads/master i: 191157: e1ed7c8 191155: 43a4a29 191151: 431e919 v: v3
git-mirror · Apr 2, 2010 · 1131322 · 1131322
1 parent 54239cb
commit 1131322
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Showing 2 changed files with 3 additions and 1 deletion.
diff --git a/[refs] b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: caaa8be3b6707cb9664e573a28b00f845ce9f32e
+refs/heads/master: 40b91cd10f000b4c4934e48e2e5c0bec66def144
diff --git a/trunk/arch/x86/kernel/cpu/perf_event_intel.c b/trunk/arch/x86/kernel/cpu/perf_event_intel.c
@@ -488,6 +488,7 @@ static void intel_pmu_enable_all(int added)
  * Workaround for:
  *   Intel Errata AAK100 (model 26)
  *   Intel Errata AAP53  (model 30)
+ *   Intel Errata BD53   (model 44)
  *
  * These chips need to be 'reset' when adding counters by programming
  * the magic three (non counting) events 0x4300D2, 0x4300B1 and 0x4300B5
@@ -980,6 +981,7 @@ static __init int intel_pmu_init(void)
 		intel_pmu_lbr_init_nhm();
 
 		x86_pmu.event_constraints = intel_westmere_event_constraints;
+		x86_pmu.enable_all = intel_pmu_nhm_enable_all;
 		pr_cont("Westmere events, ");
 		break;