---

yaml
---
r: 299603
b: refs/heads/master
c: 6bbbc30
h: refs/heads/master
i:
  299601: 39371b9
  299599: 9c35dcd
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 4d634ca35a8b38530b134ae92bc9e3cc9c23c030
+refs/heads/master: 6bbbc30ce6b0ae428575c8af7c2a6c342c534e19

trunk/MAINTAINERS

@@ -3592,7 +3592,6 @@ S:	Supported
 F:	drivers/net/wireless/iwlegacy/
 
 INTEL WIRELESS WIFI LINK (iwlwifi)
-M:	Johannes Berg <johannes.berg@intel.com>
 M:	Wey-Yi Guy <wey-yi.w.guy@intel.com>
 M:	Intel Linux Wireless <ilw@linux.intel.com>
 L:	linux-wireless@vger.kernel.org
@@ -7579,8 +7578,8 @@ F:	Documentation/filesystems/xfs.txt
 F:	fs/xfs/
 
 XILINX AXI ETHERNET DRIVER
-M:	Anirudha Sarangi <anirudh@xilinx.com>
-M:	John Linn <John.Linn@xilinx.com>
+M:	Ariane Keller <ariane.keller@tik.ee.ethz.ch>
+M:	Daniel Borkmann <daniel.borkmann@tik.ee.ethz.ch>
 S:	Maintained
 F:	drivers/net/ethernet/xilinx/xilinx_axienet*
 

trunk/arch/arm/kernel/smp_twd.c

@@ -118,10 +118,14 @@ static int twd_cpufreq_transition(struct notifier_block *nb,
 	 * The twd clock events must be reprogrammed to account for the new
 	 * frequency.  The timer is local to a cpu, so cross-call to the
 	 * changing cpu.
+	 *
+	 * Only wait for it to finish, if the cpu is active to avoid
+	 * deadlock when cpu1 is spinning on while(!cpu_active(cpu1)) during
+	 * booting of that cpu.
 	 */
 	if (state == CPUFREQ_POSTCHANGE || state == CPUFREQ_RESUMECHANGE)
 		smp_call_function_single(freqs->cpu, twd_update_frequency,
-			NULL, 1);
+					 NULL, cpu_active(freqs->cpu));
 
 	return NOTIFY_OK;
 }

trunk/arch/hexagon/kernel/dma.c

@@ -22,6 +22,7 @@
 #include <linux/bootmem.h>
 #include <linux/genalloc.h>
 #include <asm/dma-mapping.h>
+#include <linux/module.h>
 
 struct dma_map_ops *dma_ops;
 EXPORT_SYMBOL(dma_ops);

trunk/arch/hexagon/kernel/ptrace.c

@@ -28,6 +28,7 @@
 #include <linux/ptrace.h>
 #include <linux/regset.h>
 #include <linux/user.h>
+#include <linux/elf.h>
 
 #include <asm/user.h>
 

trunk/arch/hexagon/kernel/time.c

@@ -28,6 +28,7 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
+#include <linux/module.h>
 
 #include <asm/timer-regs.h>
 #include <asm/hexagon_vm.h>

trunk/arch/hexagon/kernel/vdso.c

@@ -21,6 +21,7 @@
 #include <linux/err.h>
 #include <linux/mm.h>
 #include <linux/vmalloc.h>
+#include <linux/binfmts.h>
 
 #include <asm/vdso.h>
 

trunk/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi

@@ -53,16 +53,6 @@ timer@41100 {
 		      3 0 3 0>;
 };
 
-message@41400 {
-	compatible = "fsl,mpic-v3.1-msgr";
-	reg = <0x41400 0x200>;
-	interrupts = <
-		0xb0 2 0 0
-		0xb1 2 0 0
-		0xb2 2 0 0
-		0xb3 2 0 0>;
-};
-
 msi@41600 {
 	compatible = "fsl,mpic-msi";
 	reg = <0x41600 0x80>;

trunk/arch/powerpc/include/asm/mpic.h

@@ -275,6 +275,9 @@ struct mpic
 	unsigned int		isu_mask;
 	/* Number of sources */
 	unsigned int		num_sources;
+	/* default senses array */
+	unsigned char		*senses;
+	unsigned int		senses_count;
 
 	/* vector numbers used for internal sources (ipi/timers) */
 	unsigned int		ipi_vecs[4];
@@ -412,6 +415,21 @@ extern struct mpic *mpic_alloc(struct device_node *node,
 extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
 			    phys_addr_t phys_addr);
 
+/* Set default sense codes
+ *
+ * @mpic:	controller
+ * @senses:	array of sense codes
+ * @count:	size of above array
+ *
+ * Optionally provide an array (indexed on hardware interrupt numbers
+ * for this MPIC) of default sense codes for the chip. Those are linux
+ * sense codes IRQ_TYPE_*
+ *
+ * The driver gets ownership of the pointer, don't dispose of it or
+ * anything like that. __init only.
+ */
+extern void mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count);
+
 
 /* Initialize the controller. After this has been called, none of the above
  * should be called again for this mpic

trunk/arch/powerpc/include/asm/mpic_msgr.h

@@ -13,7 +13,6 @@
 
 #include <linux/types.h>
 #include <linux/spinlock.h>
-#include <asm/smp.h>
 
 struct mpic_msgr {
 	u32 __iomem *base;

trunk/arch/powerpc/include/asm/reg_booke.h

@@ -15,6 +15,11 @@
 #ifndef __ASM_POWERPC_REG_BOOKE_H__
 #define __ASM_POWERPC_REG_BOOKE_H__
 
+#ifdef CONFIG_BOOKE_WDT
+extern u32 booke_wdt_enabled;
+extern u32 booke_wdt_period;
+#endif /* CONFIG_BOOKE_WDT */
+
 /* Machine State Register (MSR) Fields */
 #define MSR_GS		(1<<28) /* Guest state */
 #define MSR_UCLE	(1<<26)	/* User-mode cache lock enable */

trunk/arch/powerpc/kernel/setup_32.c

@@ -150,9 +150,6 @@ notrace void __init machine_init(u64 dt_ptr)
 }
 
 #ifdef CONFIG_BOOKE_WDT
-extern u32 booke_wdt_enabled;
-extern u32 booke_wdt_period;
-
 /* Checks wdt=x and wdt_period=xx command-line option */
 notrace int __init early_parse_wdt(char *p)
 {

trunk/arch/powerpc/platforms/85xx/common.c

@@ -21,12 +21,6 @@ static struct of_device_id __initdata mpc85xx_common_ids[] = {
 	{ .compatible = "fsl,qe", },
 	{ .compatible = "fsl,cpm2", },
 	{ .compatible = "fsl,srio", },
-	/* So that the DMA channel nodes can be probed individually: */
-	{ .compatible = "fsl,eloplus-dma", },
-	/* For the PMC driver */
-	{ .compatible = "fsl,mpc8548-guts", },
-	/* Probably unnecessary? */
-	{ .compatible = "gpio-leds", },
 	{},
 };
 

trunk/arch/powerpc/platforms/85xx/mpc85xx_mds.c

@@ -399,14 +399,23 @@ static int __init board_fixups(void)
 machine_arch_initcall(mpc8568_mds, board_fixups);
 machine_arch_initcall(mpc8569_mds, board_fixups);
 
+static struct of_device_id mpc85xx_ids[] = {
+	{ .compatible = "fsl,mpc8548-guts", },
+	{ .compatible = "gpio-leds", },
+	{},
+};
+
 static int __init mpc85xx_publish_devices(void)
 {
 	if (machine_is(mpc8568_mds))
 		simple_gpiochip_init("fsl,mpc8568mds-bcsr-gpio");
 	if (machine_is(mpc8569_mds))
 		simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
 
-	return mpc85xx_common_publish_devices();
+	mpc85xx_common_publish_devices();
+	of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
+
+	return 0;
 }
 
 machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);

trunk/arch/powerpc/platforms/85xx/p1022_ds.c

@@ -460,7 +460,18 @@ static void __init p1022_ds_setup_arch(void)
 	pr_info("Freescale P1022 DS reference board\n");
 }
 
-machine_device_initcall(p1022_ds, mpc85xx_common_publish_devices);
+static struct of_device_id __initdata p1022_ds_ids[] = {
+	/* So that the DMA channel nodes can be probed individually: */
+	{ .compatible = "fsl,eloplus-dma", },
+	{},
+};
+
+static int __init p1022_ds_publish_devices(void)
+{
+	mpc85xx_common_publish_devices();
+	return of_platform_bus_probe(NULL, p1022_ds_ids, NULL);
+}
+machine_device_initcall(p1022_ds, p1022_ds_publish_devices);
 
 machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier);
 

trunk/arch/powerpc/platforms/powermac/low_i2c.c

@@ -366,20 +366,11 @@ static void kw_i2c_timeout(unsigned long data)
 	unsigned long flags;
 
 	spin_lock_irqsave(&host->lock, flags);
-
-	/*
-	 * If the timer is pending, that means we raced with the
-	 * irq, in which case we just return
-	 */
-	if (timer_pending(&host->timeout_timer))
-		goto skip;
-
 	kw_i2c_handle_interrupt(host, kw_read_reg(reg_isr));
 	if (host->state != state_idle) {
 		host->timeout_timer.expires = jiffies + KW_POLL_TIMEOUT;
 		add_timer(&host->timeout_timer);
 	}
- skip:
 	spin_unlock_irqrestore(&host->lock, flags);
 }
 

trunk/arch/powerpc/platforms/pseries/eeh.c

@@ -1076,7 +1076,7 @@ static void eeh_add_device_late(struct pci_dev *dev)
 	pr_debug("EEH: Adding device %s\n", pci_name(dev));
 
 	dn = pci_device_to_OF_node(dev);
-	edev = of_node_to_eeh_dev(dn);
+	edev = pci_dev_to_eeh_dev(dev);
 	if (edev->pdev == dev) {
 		pr_debug("EEH: Already referenced !\n");
 		return;

trunk/arch/powerpc/sysdev/mpic.c

@@ -604,14 +604,18 @@ static struct mpic *mpic_find(unsigned int irq)
 }
 
 /* Determine if the linux irq is an IPI */
-static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src)
+static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
 {
+	unsigned int src = virq_to_hw(irq);
+
 	return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
 }
 
 /* Determine if the linux irq is a timer */
-static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src)
+static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int irq)
 {
+	unsigned int src = virq_to_hw(irq);
+
 	return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
 }
 
@@ -872,45 +876,21 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
 	if (src >= mpic->num_sources)
 		return -EINVAL;
 
-	vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
-
-	/* We don't support "none" type */
 	if (flow_type == IRQ_TYPE_NONE)
-		flow_type = IRQ_TYPE_DEFAULT;
-
-	/* Default: read HW settings */
-	if (flow_type == IRQ_TYPE_DEFAULT) {
-		switch(vold & (MPIC_INFO(VECPRI_POLARITY_MASK) |
-			       MPIC_INFO(VECPRI_SENSE_MASK))) {
-			case MPIC_INFO(VECPRI_SENSE_EDGE) |
-			     MPIC_INFO(VECPRI_POLARITY_POSITIVE):
-				flow_type = IRQ_TYPE_EDGE_RISING;
-				break;
-			case MPIC_INFO(VECPRI_SENSE_EDGE) |
-			     MPIC_INFO(VECPRI_POLARITY_NEGATIVE):
-				flow_type = IRQ_TYPE_EDGE_FALLING;
-				break;
-			case MPIC_INFO(VECPRI_SENSE_LEVEL) |
-			     MPIC_INFO(VECPRI_POLARITY_POSITIVE):
-				flow_type = IRQ_TYPE_LEVEL_HIGH;
-				break;
-			case MPIC_INFO(VECPRI_SENSE_LEVEL) |
-			     MPIC_INFO(VECPRI_POLARITY_NEGATIVE):
-				flow_type = IRQ_TYPE_LEVEL_LOW;
-				break;
-		}
-	}
+		if (mpic->senses && src < mpic->senses_count)
+			flow_type = mpic->senses[src];
+	if (flow_type == IRQ_TYPE_NONE)
+		flow_type = IRQ_TYPE_LEVEL_LOW;
 
-	/* Apply to irq desc */
 	irqd_set_trigger_type(d, flow_type);
 
-	/* Apply to HW */
 	if (mpic_is_ht_interrupt(mpic, src))
 		vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
 			MPIC_VECPRI_SENSE_EDGE;
 	else
 		vecpri = mpic_type_to_vecpri(mpic, flow_type);
 
+	vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
 	vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
 			MPIC_INFO(VECPRI_SENSE_MASK));
 	vnew |= vecpri;
@@ -1046,7 +1026,7 @@ static int mpic_host_map(struct irq_domain *h, unsigned int virq,
 	irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
 
 	/* Set default irq type */
-	irq_set_irq_type(virq, IRQ_TYPE_DEFAULT);
+	irq_set_irq_type(virq, IRQ_TYPE_NONE);
 
 	/* If the MPIC was reset, then all vectors have already been
 	 * initialized.  Otherwise, a per source lazy initialization
@@ -1437,6 +1417,12 @@ void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
 		mpic->num_sources = isu_first + mpic->isu_size;
 }
 
+void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
+{
+	mpic->senses = senses;
+	mpic->senses_count = count;
+}
+
 void __init mpic_init(struct mpic *mpic)
 {
 	int i, cpu;
@@ -1569,12 +1555,12 @@ void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
 		return;
 
 	raw_spin_lock_irqsave(&mpic_lock, flags);
-	if (mpic_is_ipi(mpic, src)) {
+	if (mpic_is_ipi(mpic, irq)) {
 		reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
 			~MPIC_VECPRI_PRIORITY_MASK;
 		mpic_ipi_write(src - mpic->ipi_vecs[0],
 			       reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
-	} else if (mpic_is_tm(mpic, src)) {
+	} else if (mpic_is_tm(mpic, irq)) {
 		reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
 			~MPIC_VECPRI_PRIORITY_MASK;
 		mpic_tm_write(src - mpic->timer_vecs[0],