sh: intc - fix IRQ4 and IRQ5 typo on sh3

The intc tables for sh3 currently contain a typo where the bit fields in IPRD are mixed up for IRQ4 and IRQ5. This patch makes sure the correct bit fields are used - all according to the datasheets. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
git-mirror · Sep 21, 2007 · 137b53b · 137b53b
1 parent ac38e4d
commit 137b53b
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Showing 3 changed files with 3 additions and 3 deletions.
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -75,7 +75,7 @@ static struct intc_prio_reg prio_registers[] = {
 	{ 0xfffffee2, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
 	{ 0xfffffee4, 16, 4, /* IPRB */ { WDT, REF_RCMI, 0, 0 } },
 	{ 0xa4000016, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
-	{ 0xa4000018, 16, 4, /* IPRD */ { PINT07, PINT815, IRQ4, IRQ5 } },
+	{ 0xa4000018, 16, 4, /* IPRD */ { PINT07, PINT815, IRQ5, IRQ4 } },
 	{ 0xa400001a, 16, 4, /* IPRE */ { DMAC, SCIF0, SCIF2, ADC_ADI } },
 	{ 0xa4080000, 16, 4, /* IPRF */ { 0, 0, USB } },
 	{ 0xa4080002, 16, 4, /* IPRG */ { TPU0, TPU1 } },

diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
@@ -95,7 +95,7 @@ static struct intc_prio_reg prio_registers[] = {
     defined(CONFIG_CPU_SUBTYPE_SH7707) || \
     defined(CONFIG_CPU_SUBTYPE_SH7709)
 	{ 0xa4000016, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
-	{ 0xa4000018, 16, 4, /* IPRD */ { 0, 0, IRQ4, IRQ5 } },
+	{ 0xa4000018, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
 	{ 0xa400001a, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } },
 #endif
 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \

diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -88,7 +88,7 @@ static struct intc_prio_reg prio_registers[] = {
 	{ 0xfffffee2, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
 	{ 0xfffffee4, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
 	{ 0xa4000016, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
-	{ 0xa4000018, 16, 4, /* IPRD */ { 0, 0, IRQ4, IRQ5 } },
+	{ 0xa4000018, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
 	{ 0xa400001a, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } },
 	{ 0xa4080000, 16, 4, /* IPRF */ { 0, DMAC2 } },
 #ifdef CONFIG_CPU_SUBTYPE_SH7710