---

yaml
---
r: 144528
b: refs/heads/master
c: 855c551
h: refs/heads/master
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 7ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47
+refs/heads/master: 855c551f5b8cc3815d58e1056c1f1e7c461e2d24

trunk/arch/arm/Kconfig

@@ -765,6 +765,19 @@ config ARM_ERRATA_430973
 	  Note that setting specific bits in the ACTLR register may not be
 	  available in non-secure mode.
 
+config ARM_ERRATA_458693
+	bool "ARM errata: Processor deadlock when a false hazard is created"
+	depends on CPU_V7
+	help
+	  This option enables the workaround for the 458693 Cortex-A8 (r2p0)
+	  erratum. For very specific sequences of memory operations, it is
+	  possible for a hazard condition intended for a cache line to instead
+	  be incorrectly associated with a different cache line. This false
+	  hazard might then cause a processor deadlock. The workaround enables
+	  the L1 caching of the NEON accesses and disables the PLD instruction
+	  in the ACTLR register. Note that setting specific bits in the ACTLR
+	  register may not be available in non-secure mode.
+
 endmenu
 
 source "arch/arm/common/Kconfig"

trunk/arch/arm/mm/proc-v7.S

@@ -187,6 +187,12 @@ __v7_setup:
 	mrc	p15, 0, r10, c1, c0, 1		@ read aux control register
 	orr	r10, r10, #(1 << 6)		@ set IBE to 1
 	mcr	p15, 0, r10, c1, c0, 1		@ write aux control register
+#endif
+#ifdef CONFIG_ARM_ERRATA_458693
+	mrc	p15, 0, r10, c1, c0, 1		@ read aux control register
+	orr	r10, r10, #(1 << 5)		@ set L1NEON to 1
+	orr	r10, r10, #(1 << 9)		@ set PLDNOP to 1
+	mcr	p15, 0, r10, c1, c0, 1		@ write aux control register
 #endif
 	mov	r10, #0
 #ifdef HARVARD_CACHE