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yaml
---
r: 10327
b: refs/heads/master
c: 302a5c4
h: refs/heads/master
i:
  10325: 63630da
  10323: 642f681
  10319: 99779c1
v: v3
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Ralf Baechle authored and Jeff Garzik committed Oct 18, 2005
1 parent 0fa61f5 commit 148e809
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Showing 3 changed files with 35 additions and 35 deletions.
2 changes: 1 addition & 1 deletion [refs]
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Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 2891439e7378e35534d7eb32f77671dc4d61db4c
refs/heads/master: 302a5c4b3d4d6aff7772a4b3431bb772586e6011
28 changes: 14 additions & 14 deletions trunk/drivers/net/sgiseeq.c
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Original file line number Diff line number Diff line change
Expand Up @@ -32,8 +32,6 @@

#include "sgiseeq.h"

static char *version = "sgiseeq.c: David S. Miller (dm@engr.sgi.com)\n";

static char *sgiseeqstr = "SGI Seeq8003";

/*
Expand Down Expand Up @@ -113,9 +111,9 @@ static struct net_device *root_sgiseeq_dev;

static inline void hpc3_eth_reset(struct hpc3_ethregs *hregs)
{
hregs->rx_reset = HPC3_ERXRST_CRESET | HPC3_ERXRST_CLRIRQ;
hregs->reset = HPC3_ERST_CRESET | HPC3_ERST_CLRIRQ;
udelay(20);
hregs->rx_reset = 0;
hregs->reset = 0;
}

static inline void reset_hpc3_and_seeq(struct hpc3_ethregs *hregs,
Expand Down Expand Up @@ -252,7 +250,6 @@ void sgiseeq_dump_rings(void)

#define TSTAT_INIT_SEEQ (SEEQ_TCMD_IPT|SEEQ_TCMD_I16|SEEQ_TCMD_IC|SEEQ_TCMD_IUF)
#define TSTAT_INIT_EDLC ((TSTAT_INIT_SEEQ) | SEEQ_TCMD_RB2)
#define RDMACFG_INIT (HPC3_ERXDCFG_FRXDC | HPC3_ERXDCFG_FEOP | HPC3_ERXDCFG_FIRQ)

static int init_seeq(struct net_device *dev, struct sgiseeq_private *sp,
struct sgiseeq_regs *sregs)
Expand All @@ -274,8 +271,6 @@ static int init_seeq(struct net_device *dev, struct sgiseeq_private *sp,
sregs->tstat = TSTAT_INIT_SEEQ;
}

hregs->rx_dconfig |= RDMACFG_INIT;

hregs->rx_ndptr = CPHYSADDR(sp->rx_desc);
hregs->tx_ndptr = CPHYSADDR(sp->tx_desc);

Expand Down Expand Up @@ -446,7 +441,7 @@ static irqreturn_t sgiseeq_interrupt(int irq, void *dev_id, struct pt_regs *regs
spin_lock(&sp->tx_lock);

/* Ack the IRQ and set software state. */
hregs->rx_reset = HPC3_ERXRST_CLRIRQ;
hregs->reset = HPC3_ERST_CLRIRQ;

/* Always check for received packets. */
sgiseeq_rx(dev, sp, hregs, sregs);
Expand Down Expand Up @@ -646,7 +641,7 @@ static inline void setup_rx_ring(struct sgiseeq_rx_desc *buf, int nbufs)

#define ALIGNED(x) ((((unsigned long)(x)) + 0xf) & ~(0xf))

static int sgiseeq_init(struct hpc3_regs* regs, int irq)
static int sgiseeq_init(struct hpc3_regs* hpcregs, int irq)
{
struct sgiseeq_init_block *sr;
struct sgiseeq_private *sp;
Expand Down Expand Up @@ -682,8 +677,8 @@ static int sgiseeq_init(struct hpc3_regs* regs, int irq)
gpriv = sp;
gdev = dev;
#endif
sp->sregs = (struct sgiseeq_regs *) &hpc3c0->eth_ext[0];
sp->hregs = &hpc3c0->ethregs;
sp->sregs = (struct sgiseeq_regs *) &hpcregs->eth_ext[0];
sp->hregs = &hpcregs->ethregs;
sp->name = sgiseeqstr;
sp->mode = SEEQ_RCMD_RBCAST;

Expand All @@ -700,6 +695,11 @@ static int sgiseeq_init(struct hpc3_regs* regs, int irq)
setup_rx_ring(sp->rx_desc, SEEQ_RX_BUFFERS);
setup_tx_ring(sp->tx_desc, SEEQ_TX_BUFFERS);

/* Setup PIO and DMA transfer timing */
sp->hregs->pconfig = 0x161;
sp->hregs->dconfig = HPC3_EDCFG_FIRQ | HPC3_EDCFG_FEOP |
HPC3_EDCFG_FRXDC | HPC3_EDCFG_PTO | 0x026;

/* Reset the chip. */
hpc3_eth_reset(sp->hregs);

Expand All @@ -726,7 +726,7 @@ static int sgiseeq_init(struct hpc3_regs* regs, int irq)
goto err_out_free_page;
}

printk(KERN_INFO "%s: SGI Seeq8003 ", dev->name);
printk(KERN_INFO "%s: %s ", dev->name, sgiseeqstr);
for (i = 0; i < 6; i++)
printk("%2.2x%c", dev->dev_addr[i], i == 5 ? '\n' : ':');

Expand All @@ -746,8 +746,6 @@ static int sgiseeq_init(struct hpc3_regs* regs, int irq)

static int __init sgiseeq_probe(void)
{
printk(version);

/* On board adapter on 1st HPC is always present */
return sgiseeq_init(hpc3c0, SGI_ENET_IRQ);
}
Expand All @@ -769,4 +767,6 @@ static void __exit sgiseeq_exit(void)
module_init(sgiseeq_probe);
module_exit(sgiseeq_exit);

MODULE_DESCRIPTION("SGI Seeq 8003 driver");
MODULE_AUTHOR("Linux/MIPS Mailing List <linux-mips@linux-mips.org>");
MODULE_LICENSE("GPL");
40 changes: 20 additions & 20 deletions trunk/include/asm-mips/sgi/hpc3.h
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Original file line number Diff line number Diff line change
Expand Up @@ -128,26 +128,26 @@ struct hpc3_ethregs {
volatile u32 rx_gfptr; /* current GIO fifo ptr */
volatile u32 rx_dfptr; /* current device fifo ptr */
u32 _unused1; /* padding */
volatile u32 rx_reset; /* reset register */
#define HPC3_ERXRST_CRESET 0x1 /* Reset dma channel and external controller */
#define HPC3_ERXRST_CLRIRQ 0x2 /* Clear channel interrupt */
#define HPC3_ERXRST_LBACK 0x4 /* Enable diagnostic loopback mode of Seeq8003 */

volatile u32 rx_dconfig; /* DMA configuration register */
#define HPC3_ERXDCFG_D1 0x0000f /* Cycles to spend in D1 state for PIO */
#define HPC3_ERXDCFG_D2 0x000f0 /* Cycles to spend in D2 state for PIO */
#define HPC3_ERXDCFG_D3 0x00f00 /* Cycles to spend in D3 state for PIO */
#define HPC3_ERXDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */
#define HPC3_ERXDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */
#define HPC3_ERXDCFG_FEOP 0x04000 /* Bad packet marker timeout enable */
#define HPC3_ERXDCFG_FIRQ 0x08000 /* Another bad packet timeout enable */
#define HPC3_ERXDCFG_PTO 0x30000 /* Programmed timeout value for above two */

volatile u32 rx_pconfig; /* PIO configuration register */
#define HPC3_ERXPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */
#define HPC3_ERXPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */
#define HPC3_ERXPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */
#define HPC3_ERXPCFG_TST 0x1000 /* Diagnistic ram test feature bit */
volatile u32 reset; /* reset register */
#define HPC3_ERST_CRESET 0x1 /* Reset dma channel and external controller */
#define HPC3_ERST_CLRIRQ 0x2 /* Clear channel interrupt */
#define HPC3_ERST_LBACK 0x4 /* Enable diagnostic loopback mode of Seeq8003 */

volatile u32 dconfig; /* DMA configuration register */
#define HPC3_EDCFG_D1 0x0000f /* Cycles to spend in D1 state for PIO */
#define HPC3_EDCFG_D2 0x000f0 /* Cycles to spend in D2 state for PIO */
#define HPC3_EDCFG_D3 0x00f00 /* Cycles to spend in D3 state for PIO */
#define HPC3_EDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */
#define HPC3_EDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */
#define HPC3_EDCFG_FEOP 0x04000 /* Bad packet marker timeout enable */
#define HPC3_EDCFG_FIRQ 0x08000 /* Another bad packet timeout enable */
#define HPC3_EDCFG_PTO 0x30000 /* Programmed timeout value for above two */

volatile u32 pconfig; /* PIO configuration register */
#define HPC3_EPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */
#define HPC3_EPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */
#define HPC3_EPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */
#define HPC3_EPCFG_TST 0x1000 /* Diagnistic ram test feature bit */

u32 _unused2[0x1000/4 - 8]; /* padding */

Expand Down

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