---

yaml
---
r: 165773
b: refs/heads/master
c: ad643f5
h: refs/heads/master
i:
  165771: 7dfe621
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 345d852391cf3fdc73f23a9ca522c6e7b5eb5a52
+refs/heads/master: ad643f54c8514998333bc6c7b201fda2267496be

trunk/drivers/dma/ioat/dma.c

@@ -396,7 +396,7 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
 	dump_desc_dbg(ioat, chain_tail);
 	dump_desc_dbg(ioat, first);
 
-	ioat->pending += desc->tx_cnt;
+	ioat->pending += desc->hw->tx_cnt;
 	if (ioat->pending >= ioat_pending_level)
 		__ioat1_dma_memcpy_issue_pending(ioat);
 	spin_unlock_bh(&ioat->desc_lock);
@@ -655,11 +655,11 @@ ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest,
 	spin_unlock_bh(&ioat->desc_lock);
 
 	desc->txd.flags = flags;
-	desc->tx_cnt = tx_cnt;
 	desc->len = total_len;
 	list_splice(&chain, &desc->txd.tx_list);
 	hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
 	hw->ctl_f.compl_write = 1;
+	hw->tx_cnt = tx_cnt;
 	dump_desc_dbg(ioat, desc);
 
 	return &desc->txd;

trunk/drivers/dma/ioat/dma.h

@@ -165,14 +165,12 @@ ioat_is_complete(struct dma_chan *c, dma_cookie_t cookie,
  * @hw: hardware DMA descriptor
  * @node: this descriptor will either be on the free list,
  *     or attached to a transaction list (async_tx.tx_list)
- * @tx_cnt: number of descriptors required to complete the transaction
  * @txd: the generic software descriptor for all engines
  * @id: identifier for debug
  */
 struct ioat_desc_sw {
 	struct ioat_dma_descriptor *hw;
 	struct list_head node;
-	int tx_cnt;
 	size_t len;
 	struct dma_async_tx_descriptor txd;
 	#ifdef DEBUG

trunk/drivers/dma/ioat/hw.h

@@ -63,7 +63,11 @@ struct ioat_dma_descriptor {
 	uint64_t	next;
 	uint64_t	rsv1;
 	uint64_t	rsv2;
-	uint64_t	user1;
+	/* store some driver data in an unused portion of the descriptor */
+	union {
+		uint64_t	user1;
+		uint64_t	tx_cnt;
+	};
 	uint64_t	user2;
 };
 #endif