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qlcnic: modify PCI and register access routines
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Refactor 82xx driver to support new adapter
Update PCI and hardware access routines

Signed-off-by: Anirban Chakraborty <anirban.chakraborty@qlogic.com>
Signed-off-by: Sony Chacko <sony.chacko@qlogic.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Sony Chacko authored and David S. Miller committed Dec 4, 2012
1 parent 7978845 commit 15087c2
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Showing 4 changed files with 222 additions and 162 deletions.
4 changes: 2 additions & 2 deletions drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1279,7 +1279,7 @@ struct qlcnic_cmd_args {
int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter);
int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config);

u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off);
int qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off);
int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *, ulong off, u32 data);
int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
Expand Down Expand Up @@ -1345,7 +1345,7 @@ int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);

void __iomem *qlcnic_get_ioaddr(struct qlcnic_adapter *, u32);
void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *, u32);

int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
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40 changes: 24 additions & 16 deletions drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h
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Original file line number Diff line number Diff line change
Expand Up @@ -816,55 +816,63 @@ enum {
#define LSD(x) ((uint32_t)((uint64_t)(x)))
#define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))

#define QLCNIC_MS_CTRL 0x41000090
#define QLCNIC_MS_ADDR_LO 0x41000094
#define QLCNIC_MS_ADDR_HI 0x41000098
#define QLCNIC_MS_WRTDATA_LO 0x410000A0
#define QLCNIC_MS_WRTDATA_HI 0x410000A4
#define QLCNIC_MS_WRTDATA_ULO 0x410000B0
#define QLCNIC_MS_WRTDATA_UHI 0x410000B4
#define QLCNIC_MS_RDDATA_LO 0x410000A8
#define QLCNIC_MS_RDDATA_HI 0x410000AC
#define QLCNIC_MS_RDDATA_ULO 0x410000B8
#define QLCNIC_MS_RDDATA_UHI 0x410000BC

#define QLCNIC_TA_WRITE_ENABLE (TA_CTL_ENABLE | TA_CTL_WRITE)
#define QLCNIC_TA_WRITE_START (TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE)
#define QLCNIC_TA_START_ENABLE (TA_CTL_START | TA_CTL_ENABLE)

#define QLCNIC_LEGACY_INTR_CONFIG \
{ \
{ \
.int_vec_bit = PCIX_INT_VECTOR_BIT_F0, \
.tgt_status_reg = ISR_INT_TARGET_STATUS, \
.tgt_mask_reg = ISR_INT_TARGET_MASK, \
.pci_int_reg = ISR_MSI_INT_TRIGGER(0) }, \
.tgt_mask_reg = ISR_INT_TARGET_MASK, }, \
\
{ \
.int_vec_bit = PCIX_INT_VECTOR_BIT_F1, \
.tgt_status_reg = ISR_INT_TARGET_STATUS_F1, \
.tgt_mask_reg = ISR_INT_TARGET_MASK_F1, \
.pci_int_reg = ISR_MSI_INT_TRIGGER(1) }, \
.tgt_mask_reg = ISR_INT_TARGET_MASK_F1, }, \
\
{ \
.int_vec_bit = PCIX_INT_VECTOR_BIT_F2, \
.tgt_status_reg = ISR_INT_TARGET_STATUS_F2, \
.tgt_mask_reg = ISR_INT_TARGET_MASK_F2, \
.pci_int_reg = ISR_MSI_INT_TRIGGER(2) }, \
.tgt_mask_reg = ISR_INT_TARGET_MASK_F2, }, \
\
{ \
.int_vec_bit = PCIX_INT_VECTOR_BIT_F3, \
.tgt_status_reg = ISR_INT_TARGET_STATUS_F3, \
.tgt_mask_reg = ISR_INT_TARGET_MASK_F3, \
.pci_int_reg = ISR_MSI_INT_TRIGGER(3) }, \
.tgt_mask_reg = ISR_INT_TARGET_MASK_F3, }, \
\
{ \
.int_vec_bit = PCIX_INT_VECTOR_BIT_F4, \
.tgt_status_reg = ISR_INT_TARGET_STATUS_F4, \
.tgt_mask_reg = ISR_INT_TARGET_MASK_F4, \
.pci_int_reg = ISR_MSI_INT_TRIGGER(4) }, \
.tgt_mask_reg = ISR_INT_TARGET_MASK_F4, }, \
\
{ \
.int_vec_bit = PCIX_INT_VECTOR_BIT_F5, \
.tgt_status_reg = ISR_INT_TARGET_STATUS_F5, \
.tgt_mask_reg = ISR_INT_TARGET_MASK_F5, \
.pci_int_reg = ISR_MSI_INT_TRIGGER(5) }, \
.tgt_mask_reg = ISR_INT_TARGET_MASK_F5, }, \
\
{ \
.int_vec_bit = PCIX_INT_VECTOR_BIT_F6, \
.tgt_status_reg = ISR_INT_TARGET_STATUS_F6, \
.tgt_mask_reg = ISR_INT_TARGET_MASK_F6, \
.pci_int_reg = ISR_MSI_INT_TRIGGER(6) }, \
.tgt_mask_reg = ISR_INT_TARGET_MASK_F6, }, \
\
{ \
.int_vec_bit = PCIX_INT_VECTOR_BIT_F7, \
.tgt_status_reg = ISR_INT_TARGET_STATUS_F7, \
.tgt_mask_reg = ISR_INT_TARGET_MASK_F7, \
.pci_int_reg = ISR_MSI_INT_TRIGGER(7) }, \
.tgt_mask_reg = ISR_INT_TARGET_MASK_F7, }, \
}

/* NIU REGS */
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