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yaml
---
r: 307273
b: refs/heads/master
c: 8512e07
h: refs/heads/master
i:
  307271: 985ffb2
v: v3
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Alan Cox authored and Dave Airlie committed May 11, 2012
1 parent 4bb1a76 commit 1575f5d
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Showing 6 changed files with 269 additions and 2 deletions.
2 changes: 1 addition & 1 deletion [refs]
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Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: f693dfb72db94cedd5fd2f788b4f2a7c814476de
refs/heads/master: 8512e0748729a49d9af6693f920c1b432796fa8d
53 changes: 53 additions & 0 deletions trunk/drivers/gpu/drm/gma500/cdv_device.c
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Expand Up @@ -485,10 +485,63 @@ static void cdv_hotplug_enable(struct drm_device *dev, bool on)
}
}

/* Cedarview */
static const struct psb_offset cdv_regmap[2] = {
{
.fp0 = FPA0,
.fp1 = FPA1,
.cntr = DSPACNTR,
.conf = PIPEACONF,
.src = PIPEASRC,
.dpll = DPLL_A,
.htotal = HTOTAL_A,
.hblank = HBLANK_A,
.hsync = HSYNC_A,
.vtotal = VTOTAL_A,
.vblank = VBLANK_A,
.vsync = VSYNC_A,
.stride = DSPASTRIDE,
.size = DSPASIZE,
.pos = DSPAPOS,
.base = DSPABASE,
.surf = DSPASURF,
.addr = DSPABASE,
.status = PIPEASTAT,
.linoff = DSPALINOFF,
.tileoff = DSPATILEOFF,
.palette = PALETTE_A,
},
{
.fp0 = FPB0,
.fp1 = FPB1,
.cntr = DSPBCNTR,
.conf = PIPEBCONF,
.src = PIPEBSRC,
.dpll = DPLL_B,
.htotal = HTOTAL_B,
.hblank = HBLANK_B,
.hsync = HSYNC_B,
.vtotal = VTOTAL_B,
.vblank = VBLANK_B,
.vsync = VSYNC_B,
.stride = DSPBSTRIDE,
.size = DSPBSIZE,
.pos = DSPBPOS,
.base = DSPBBASE,
.surf = DSPBSURF,
.addr = DSPBBASE,
.status = PIPEBSTAT,
.linoff = DSPBLINOFF,
.tileoff = DSPBTILEOFF,
.palette = PALETTE_B,
}
};

static int cdv_chip_setup(struct drm_device *dev)
{
struct drm_psb_private *dev_priv = dev->dev_private;
INIT_WORK(&dev_priv->hotplug_work, cdv_hotplug_work_func);
dev_priv->regmap = cdv_regmap;
cdv_get_core_freq(dev);
psb_intel_opregion_init(dev);
psb_intel_init_bios(dev);
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80 changes: 79 additions & 1 deletion trunk/drivers/gpu/drm/gma500/mdfld_device.c
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Expand Up @@ -559,6 +559,84 @@ static int mdfld_power_up(struct drm_device *dev)
return 0;
}

/* Medfield */
static const struct psb_offset mdfld_regmap[3] = {
{
.fp0 = MRST_FPA0,
.fp1 = MRST_FPA1,
.cntr = DSPACNTR,
.conf = PIPEACONF,
.src = PIPEASRC,
.dpll = MRST_DPLL_A,
.htotal = HTOTAL_A,
.hblank = HBLANK_A,
.hsync = HSYNC_A,
.vtotal = VTOTAL_A,
.vblank = VBLANK_A,
.vsync = VSYNC_A,
.stride = DSPASTRIDE,
.size = DSPASIZE,
.pos = DSPAPOS,
.surf = DSPASURF,
.addr = DSPABASE,
.status = PIPEASTAT,
.linoff = DSPALINOFF,
.tileoff = DSPATILEOFF,
.palette = PALETTE_A,
},
{
.fp0 = MDFLD_DPLL_DIV0,
.cntr = DSPBCNTR,
.conf = PIPEBCONF,
.src = PIPEBSRC,
.dpll = MDFLD_DPLL_B,
.htotal = HTOTAL_B,
.hblank = HBLANK_B,
.hsync = HSYNC_B,
.vtotal = VTOTAL_B,
.vblank = VBLANK_B,
.vsync = VSYNC_B,
.stride = DSPBSTRIDE,
.size = DSPBSIZE,
.pos = DSPBPOS,
.surf = DSPBSURF,
.addr = DSPBBASE,
.status = PIPEBSTAT,
.linoff = DSPBLINOFF,
.tileoff = DSPBTILEOFF,
.palette = PALETTE_B,
},
{
.cntr = DSPCCNTR,
.conf = PIPECCONF,
.src = PIPECSRC,
/* No DPLL_C */
.dpll = MRST_DPLL_A,
.htotal = HTOTAL_C,
.hblank = HBLANK_C,
.hsync = HSYNC_C,
.vtotal = VTOTAL_C,
.vblank = VBLANK_C,
.vsync = VSYNC_C,
.stride = DSPCSTRIDE,
.size = DSPBSIZE,
.pos = DSPCPOS,
.surf = DSPCSURF,
.addr = DSPCBASE,
.status = PIPECSTAT,
.linoff = DSPCLINOFF,
.tileoff = DSPCTILEOFF,
.palette = PALETTE_C,
},
};

static int mdfld_chip_setup(struct drm_device *dev)
{
struct drm_psb_private *dev_priv = dev->dev_private;
dev_priv->regmap = mdfld_regmap;
return mid_chip_setup(dev);
}

const struct psb_ops mdfld_chip_ops = {
.name = "mdfld",
.accel_2d = 0,
Expand All @@ -568,7 +646,7 @@ const struct psb_ops mdfld_chip_ops = {
.hdmi_mask = (1 << 1),
.sgx_offset = MRST_SGX_OFFSET,

.chip_setup = mid_chip_setup,
.chip_setup = mdfld_chip_setup,
.crtc_helper = &mdfld_helper_funcs,
.crtc_funcs = &psb_intel_crtc_funcs,

Expand Down
51 changes: 51 additions & 0 deletions trunk/drivers/gpu/drm/gma500/oaktrail_device.c
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Original file line number Diff line number Diff line change
Expand Up @@ -456,11 +456,62 @@ static int oaktrail_power_up(struct drm_device *dev)
return 0;
}

/* Oaktrail */
static const struct psb_offset oaktrail_regmap[2] = {
{
.fp0 = MRST_FPA0,
.fp1 = MRST_FPA1,
.cntr = DSPACNTR,
.conf = PIPEACONF,
.src = PIPEASRC,
.dpll = MRST_DPLL_A,
.htotal = HTOTAL_A,
.hblank = HBLANK_A,
.hsync = HSYNC_A,
.vtotal = VTOTAL_A,
.vblank = VBLANK_A,
.vsync = VSYNC_A,
.stride = DSPASTRIDE,
.size = DSPASIZE,
.pos = DSPAPOS,
.surf = DSPASURF,
.addr = DSPABASE,
.status = PIPEASTAT,
.linoff = DSPALINOFF,
.tileoff = DSPATILEOFF,
.palette = PALETTE_A,
},
{
.fp0 = FPB0,
.fp1 = FPB1,
.cntr = DSPBCNTR,
.conf = PIPEBCONF,
.src = PIPEBSRC,
.dpll = DPLL_B,
.htotal = HTOTAL_B,
.hblank = HBLANK_B,
.hsync = HSYNC_B,
.vtotal = VTOTAL_B,
.vblank = VBLANK_B,
.vsync = VSYNC_B,
.stride = DSPBSTRIDE,
.size = DSPBSIZE,
.pos = DSPBPOS,
.surf = DSPBSURF,
.addr = DSPBBASE,
.status = PIPEBSTAT,
.linoff = DSPBLINOFF,
.tileoff = DSPBTILEOFF,
.palette = PALETTE_B,
},
};

static int oaktrail_chip_setup(struct drm_device *dev)
{
struct drm_psb_private *dev_priv = dev->dev_private;
int ret;

dev_priv->regmap = oaktrail_regmap;

ret = mid_chip_setup(dev);
if (ret < 0)
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54 changes: 54 additions & 0 deletions trunk/drivers/gpu/drm/gma500/psb_device.c
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Original file line number Diff line number Diff line change
Expand Up @@ -289,8 +289,62 @@ static void psb_get_core_freq(struct drm_device *dev)
}
}

/* Poulsbo */
static const struct psb_offset psb_regmap[2] = {
{
.fp0 = FPA0,
.fp1 = FPA1,
.cntr = DSPACNTR,
.conf = PIPEACONF,
.src = PIPEASRC,
.dpll = DPLL_A,
.htotal = HTOTAL_A,
.hblank = HBLANK_A,
.hsync = HSYNC_A,
.vtotal = VTOTAL_A,
.vblank = VBLANK_A,
.vsync = VSYNC_A,
.stride = DSPASTRIDE,
.size = DSPASIZE,
.pos = DSPAPOS,
.base = DSPABASE,
.surf = DSPASURF,
.addr = DSPABASE,
.status = PIPEASTAT,
.linoff = DSPALINOFF,
.tileoff = DSPATILEOFF,
.palette = PALETTE_A,
},
{
.fp0 = FPB0,
.fp1 = FPB1,
.cntr = DSPBCNTR,
.conf = PIPEBCONF,
.src = PIPEBSRC,
.dpll = DPLL_B,
.htotal = HTOTAL_B,
.hblank = HBLANK_B,
.hsync = HSYNC_B,
.vtotal = VTOTAL_B,
.vblank = VBLANK_B,
.vsync = VSYNC_B,
.stride = DSPBSTRIDE,
.size = DSPBSIZE,
.pos = DSPBPOS,
.base = DSPBBASE,
.surf = DSPBSURF,
.addr = DSPBBASE,
.status = PIPEBSTAT,
.linoff = DSPBLINOFF,
.tileoff = DSPBTILEOFF,
.palette = PALETTE_B,
}
};

static int psb_chip_setup(struct drm_device *dev)
{
struct drm_psb_private *dev_priv = dev->dev_private;
dev_priv->regmap = psb_regmap;
psb_get_core_freq(dev);
gma_intel_setup_gmbus(dev);
psb_intel_opregion_init(dev);
Expand Down
31 changes: 31 additions & 0 deletions trunk/drivers/gpu/drm/gma500/psb_drv.h
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Original file line number Diff line number Diff line change
Expand Up @@ -280,6 +280,36 @@ struct intel_gmbus {
u32 reg0;
};

/*
* Register offset maps
*/

struct psb_offset {
u32 fp0;
u32 fp1;
u32 cntr;
u32 conf;
u32 src;
u32 dpll;
u32 dpll_md;
u32 htotal;
u32 hblank;
u32 hsync;
u32 vtotal;
u32 vblank;
u32 vsync;
u32 stride;
u32 size;
u32 pos;
u32 surf;
u32 addr;
u32 base;
u32 status;
u32 linoff;
u32 tileoff;
u32 palette;
};

/*
* Register save state. This is used to hold the context when the
* device is powered off. In the case of Oaktrail this can (but does not
Expand Down Expand Up @@ -424,6 +454,7 @@ struct psb_ops;
struct drm_psb_private {
struct drm_device *dev;
const struct psb_ops *ops;
const struct psb_offset *regmap;

struct child_device_config *child_dev;
int child_dev_num;
Expand Down

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