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yaml
---
r: 246980
b: refs/heads/master
c: 0aebff4
h: refs/heads/master
v: v3
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Matt Carlson authored and David S. Miller committed Apr 26, 2011
1 parent 46e3b50 commit 15f4d92
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Showing 3 changed files with 5 additions and 1 deletion.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: bf734843120b905bacc3d24c88d7455ae70bf6e1
refs/heads/master: 0aebff4871d26410ae485b521870bb0ffe1736f0
3 changes: 3 additions & 0 deletions trunk/drivers/net/tg3.c
Original file line number Diff line number Diff line change
Expand Up @@ -8198,6 +8198,9 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
val |= DMA_RWCTRL_TAGGED_STAT_WA;
tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
} else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
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1 change: 1 addition & 0 deletions trunk/drivers/net/tg3.h
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Expand Up @@ -188,6 +188,7 @@
#define METAL_REV_B2 0x02
#define TG3PCI_DMA_RW_CTRL 0x0000006c
#define DMA_RWCTRL_DIS_CACHE_ALIGNMENT 0x00000001
#define DMA_RWCTRL_TAGGED_STAT_WA 0x00000080
#define DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380
#define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700
#define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000
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