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drm/i915: allow 945 to control self refresh (CxSR) automatically
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I changed 945's self refresh to work without the need for the driver to
enable/disable self refresh manually based on the idle state of the gpu.
This is much better than enabling/disabling self refresh for various
reasons, including staying in a lower power state for more time and
avoiding the need for cpu cycles.

This was originally done manually to workaround issues with the hardware
hanging. However, since 9440012: drm/i915: enable low power render
writes on GEN3 hardware, automatic CxSR seems stable.

Signed-off-by: Alexander Lam <lambchop468@gmail.com>
Acked-by : Li Peng <peng.li@linux.intel.com>
[ickle: play safe with the ordering and disable CxSR before tweaking any
watermark and enable afterwards.]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Alexander Lam authored and Chris Wilson committed Jan 19, 2011
1 parent b0b544c commit 18b2190
Showing 1 changed file with 24 additions and 38 deletions.
62 changes: 24 additions & 38 deletions drivers/gpu/drm/i915/intel_display.c
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Original file line number Diff line number Diff line change
Expand Up @@ -3761,7 +3761,7 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
int planea_wm, planeb_wm;
struct intel_watermark_params planea_params, planeb_params;
unsigned long line_time_us;
int sr_clock, sr_entries = 0;
int sr_clock, sr_entries = 0, sr_enabled = 0;

/* Create copies of the base settings for each pipe */
if (IS_CRESTLINE(dev) || IS_I945GM(dev))
Expand Down Expand Up @@ -3790,6 +3790,12 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
*/
cwm = 2;

/* Play safe and disable self-refresh before adjusting watermarks. */
if (IS_I945G(dev) || IS_I945GM(dev))
I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
else if (IS_I915GM(dev))
I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);

/* Calc sr entries for one plane configs */
if (HAS_FW_BLC(dev) && sr_hdisplay &&
(!planea_clock || !planeb_clock)) {
Expand All @@ -3809,20 +3815,12 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
srwm = 1;

if (IS_I945G(dev) || IS_I945GM(dev))
I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
else if (IS_I915GM(dev)) {
/* 915M has a smaller SRWM field */
I915_WRITE(FW_BLC_SELF,
FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
else if (IS_I915GM(dev))
I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
}
} else {
/* Turn off self refresh if both pipes are enabled */
if (IS_I945G(dev) || IS_I945GM(dev)) {
I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
& ~FW_BLC_SELF_EN);
} else if (IS_I915GM(dev)) {
I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
}

sr_enabled = 1;
}

DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
Expand All @@ -3837,6 +3835,16 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,

I915_WRITE(FW_BLC, fwater_lo);
I915_WRITE(FW_BLC2, fwater_hi);

if (sr_enabled) {
if (IS_I945G(dev) || IS_I945GM(dev))
I915_WRITE(FW_BLC_SELF,
FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
else if (IS_I915GM(dev))
I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
DRM_DEBUG_KMS("memory self refresh enabled\n");
} else
DRM_DEBUG_KMS("memory self refresh disabled\n");
}

static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
Expand Down Expand Up @@ -5586,7 +5594,6 @@ static void intel_idle_update(struct work_struct *work)
struct drm_device *dev = dev_priv->dev;
struct drm_crtc *crtc;
struct intel_crtc *intel_crtc;
int enabled = 0;

if (!i915_powersave)
return;
Expand All @@ -5600,16 +5607,11 @@ static void intel_idle_update(struct work_struct *work)
if (!crtc->fb)
continue;

enabled++;
intel_crtc = to_intel_crtc(crtc);
if (!intel_crtc->busy)
intel_decrease_pllclock(crtc);
}

if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
}

mutex_unlock(&dev->struct_mutex);
}
Expand All @@ -5634,17 +5636,9 @@ void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
if (!drm_core_check_feature(dev, DRIVER_MODESET))
return;

if (!dev_priv->busy) {
if (IS_I945G(dev) || IS_I945GM(dev)) {
u32 fw_blc_self;

DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
fw_blc_self = I915_READ(FW_BLC_SELF);
fw_blc_self &= ~FW_BLC_SELF_EN;
I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
}
if (!dev_priv->busy)
dev_priv->busy = true;
} else
else
mod_timer(&dev_priv->idle_timer, jiffies +
msecs_to_jiffies(GPU_IDLE_TIMEOUT));

Expand All @@ -5656,14 +5650,6 @@ void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
intel_fb = to_intel_framebuffer(crtc->fb);
if (intel_fb->obj == obj) {
if (!intel_crtc->busy) {
if (IS_I945G(dev) || IS_I945GM(dev)) {
u32 fw_blc_self;

DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
fw_blc_self = I915_READ(FW_BLC_SELF);
fw_blc_self &= ~FW_BLC_SELF_EN;
I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
}
/* Non-busy -> busy, upclock */
intel_increase_pllclock(crtc);
intel_crtc->busy = true;
Expand Down

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