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yaml
---
r: 170573
b: refs/heads/master
c: 193cd45
h: refs/heads/master
i:
  170571: c8c9e72
v: v3
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Sujith authored and John W. Linville committed Oct 7, 2009
1 parent cf0b114 commit 1a99d05
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Showing 5 changed files with 49 additions and 13 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 0b98eaaa02965fb06dee4ad8c605bb3c93df2c98
refs/heads/master: 193cd4585e6c5650875e98ccfef2fa93616fef30
10 changes: 10 additions & 0 deletions trunk/drivers/net/wireless/ath/ath9k/hw.c
Original file line number Diff line number Diff line change
Expand Up @@ -943,6 +943,16 @@ int ath9k_hw_init(struct ath_hw *ah)
else
ath9k_hw_disablepcie(ah);

/* Support for Japan ch.14 (2484) spread */
if (AR_SREV_9287_11_OR_LATER(ah)) {
INIT_INI_ARRAY(&ah->iniCckfirNormal,
ar9287Common_normal_cck_fir_coeff_92871_1,
ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
ar9287Common_japan_2484_cck_fir_coeff_92871_1,
ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
}

r = ath9k_hw_post_init(ah);
if (r)
return r;
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2 changes: 2 additions & 0 deletions trunk/drivers/net/wireless/ath/ath9k/hw.h
Original file line number Diff line number Diff line change
Expand Up @@ -592,6 +592,8 @@ struct ath_hw {
struct ar5416IniArray iniModesAdditional;
struct ar5416IniArray iniModesRxGain;
struct ar5416IniArray iniModesTxGain;
struct ar5416IniArray iniCckfirNormal;
struct ar5416IniArray iniCckfirJapan2484;

u32 intr_gen_timer_trigger;
u32 intr_gen_timer_thresh;
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23 changes: 18 additions & 5 deletions trunk/drivers/net/wireless/ath/ath9k/initvals.h
Original file line number Diff line number Diff line change
Expand Up @@ -5918,9 +5918,6 @@ static const u_int32_t ar9287Common_9287_1_1[][2] = {
{ 0x000099ec, 0x0cc80caa },
{ 0x000099f0, 0x00000000 },
{ 0x000099fc, 0x00001042 },
{ 0x0000a1f4, 0x00fffeff },
{ 0x0000a1f8, 0x00f5f9ff },
{ 0x0000a1fc, 0xb79f6427 },
{ 0x0000a208, 0x803e4788 },
{ 0x0000a210, 0x4080a333 },
{ 0x0000a214, 0x40206c10 },
Expand Down Expand Up @@ -5980,7 +5977,7 @@ static const u_int32_t ar9287Common_9287_1_1[][2] = {
{ 0x0000b3f4, 0x00000000 },
{ 0x0000a7d8, 0x000003f1 },
{ 0x00007800, 0x00000800 },
{ 0x00007804, 0x6c35ffc2 },
{ 0x00007804, 0x6c35ffd2 },
{ 0x00007808, 0x6db6c000 },
{ 0x0000780c, 0x6db6cb30 },
{ 0x00007810, 0x6db6cb6c },
Expand All @@ -6000,7 +5997,7 @@ static const u_int32_t ar9287Common_9287_1_1[][2] = {
{ 0x00007848, 0x934934a8 },
{ 0x00007850, 0x00000000 },
{ 0x00007854, 0x00000800 },
{ 0x00007858, 0x6c35ffc2 },
{ 0x00007858, 0x6c35ffd2 },
{ 0x0000785c, 0x6db6c000 },
{ 0x00007860, 0x6db6cb30 },
{ 0x00007864, 0x6db6cb6c },
Expand All @@ -6027,6 +6024,22 @@ static const u_int32_t ar9287Common_9287_1_1[][2] = {
{ 0x000078b8, 0x2a850160 },
};

/*
* For Japanese regulatory requirements, 2484 MHz requires the following three
* registers be programmed differently from the channel between 2412 and 2472 MHz.
*/
static const u_int32_t ar9287Common_normal_cck_fir_coeff_92871_1[][2] = {
{ 0x0000a1f4, 0x00fffeff },
{ 0x0000a1f8, 0x00f5f9ff },
{ 0x0000a1fc, 0xb79f6427 },
};

static const u_int32_t ar9287Common_japan_2484_cck_fir_coeff_92871_1[][2] = {
{ 0x0000a1f4, 0x00000000 },
{ 0x0000a1f8, 0xefff0301 },
{ 0x0000a1fc, 0xca9228ee },
};

static const u_int32_t ar9287Modes_tx_gain_9287_1_1[][6] = {
/* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
{ 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
Expand Down
25 changes: 18 additions & 7 deletions trunk/drivers/net/wireless/ath/ath9k/phy.c
Original file line number Diff line number Diff line change
Expand Up @@ -113,20 +113,31 @@ void ath9k_hw_ar9280_set_channel(struct ath_hw *ah,

if (freq < 4800) {
u32 txctl;
int regWrites = 0;

bMode = 1;
fracMode = 1;
aModeRefSel = 0;
channelSel = (freq * 0x10000) / 15;

txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
if (freq == 2484) {

REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
if (AR_SREV_9287_11_OR_LATER(ah)) {
if (freq == 2484) {
REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
1, regWrites);
} else {
REG_WRITE_ARRAY(&ah->iniCckfirNormal,
1, regWrites);
}
} else {
REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
if (freq == 2484) {
/* Enable channel spreading for channel 14 */
REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
} else {
REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
}
}
} else {
bMode = 0;
Expand Down

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