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yaml
---
r: 293589
b: refs/heads/master
c: 5f7f726
h: refs/heads/master
i:
  293587: af24eb4
v: v3
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Paulo Zanoni authored and Daniel Vetter committed Feb 10, 2012
1 parent db3fbec commit 1b79f6e
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Showing 3 changed files with 13 additions and 3 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 75c13993db592343bda1fd62f2555fea037d56bd
refs/heads/master: 5f7f726d2caf1e51a39872e5a30b6984235d388e
2 changes: 2 additions & 0 deletions trunk/drivers/gpu/drm/i915/i915_reg.h
Original file line number Diff line number Diff line change
Expand Up @@ -3362,7 +3362,9 @@
#define TRANS_FSYNC_DELAY_HB4 (3<<27)
#define TRANS_DP_AUDIO_ONLY (1<<26)
#define TRANS_DP_VIDEO_AUDIO (0<<26)
#define TRANS_INTERLACE_MASK (7<<21)
#define TRANS_PROGRESSIVE (0<<21)
#define TRANS_INTERLACED (3<<21)
#define TRANS_8BPC (0<<5)
#define TRANS_10BPC (1<<5)
#define TRANS_6BPC (2<<5)
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12 changes: 10 additions & 2 deletions trunk/drivers/gpu/drm/i915/intel_display.c
Original file line number Diff line number Diff line change
Expand Up @@ -1266,7 +1266,7 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
int reg;
u32 val;
u32 val, pipeconf_val;

/* PCH only available on ILK+ */
BUG_ON(dev_priv->info->gen < 5);
Expand All @@ -1280,15 +1280,23 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,

reg = TRANSCONF(pipe);
val = I915_READ(reg);
pipeconf_val = I915_READ(PIPECONF(pipe));

if (HAS_PCH_IBX(dev_priv->dev)) {
/*
* make the BPC in transcoder be consistent with
* that in pipeconf reg.
*/
val &= ~PIPE_BPC_MASK;
val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
val |= pipeconf_val & PIPE_BPC_MASK;
}

val &= ~TRANS_INTERLACE_MASK;
if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
val |= TRANS_INTERLACED;
else
val |= TRANS_PROGRESSIVE;

I915_WRITE(reg, val | TRANS_ENABLE);
if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
DRM_ERROR("failed to enable transcoder %d\n", pipe);
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