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yaml
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r: 153888
b: refs/heads/master
c: 986d6c1
h: refs/heads/master
v: v3
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Yi Li authored and Mike Frysinger committed Jun 23, 2009
1 parent 61a167e commit 1d2ea28
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2 changes: 1 addition & 1 deletion [refs]
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refs/heads/master: bd854c077e660b5f44b5049219645042bcba61ac
refs/heads/master: 986d6c1e05642edac81cb8cc99f36a26d16ef220
4 changes: 1 addition & 3 deletions trunk/arch/blackfin/include/asm/traps.h
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Expand Up @@ -111,9 +111,7 @@
level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
#define EXC_0x2A(level) \
"Instruction fetch misaligned address violation\n" \
level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \
level " exception, the return address provided in RETX is the destination address which is\n" \
level " misaligned, rather than the address of the offending instruction.\n"
level " - Attempted misaligned instruction cache fetch.\n"
#define EXC_0x2B(level) \
"CPLB protection violation\n" \
level " - Illegal instruction fetch access (memory protection violation).\n"
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