---

yaml --- r: 326644 b: refs/heads/master c: b78c030 h: refs/heads/master v: v3
git-mirror · Sep 6, 2012 · 1dd941a · 1dd941a
1 parent 9a712f9
commit 1dd941a
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Showing 5 changed files with 14 additions and 4 deletions.
diff --git a/[refs] b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 1dfacc1613d088a99ac0360f6e276cad7f7cdf0c
+refs/heads/master: b78c030cebdaf8da14b44a4454146a7919e763a8
diff --git a/trunk/arch/arm/mach-tegra/tegra20_clocks.c b/trunk/arch/arm/mach-tegra/tegra20_clocks.c
@@ -231,6 +231,16 @@ static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
 	return divider_u16 - 1;
 }
 
+static unsigned long tegra_clk_fixed_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	return to_clk_tegra(hw)->fixed_rate;
+}
+
+struct clk_ops tegra_clk_32k_ops = {
+	.recalc_rate = tegra_clk_fixed_recalc_rate,
+};
+
 /* clk_m functions */
 static unsigned long tegra20_clk_m_recalc_rate(struct clk_hw *hw,
 			unsigned long prate)

diff --git a/trunk/arch/arm/mach-tegra/tegra30_clocks.c b/trunk/arch/arm/mach-tegra/tegra30_clocks.c
@@ -478,7 +478,7 @@ static unsigned long tegra30_clk_fixed_recalc_rate(struct clk_hw *hw,
 	return to_clk_tegra(hw)->fixed_rate;
 }
 
-struct clk_ops tegra_clk_32k_ops = {
+struct clk_ops tegra30_clk_32k_ops = {
 	.recalc_rate = tegra30_clk_fixed_recalc_rate,
 };
 

diff --git a/trunk/arch/arm/mach-tegra/tegra30_clocks.h b/trunk/arch/arm/mach-tegra/tegra30_clocks.h
@@ -17,7 +17,7 @@
 #ifndef __MACH_TEGRA30_CLOCK_H
 #define __MACH_TEGRA30_CLOCK_H
 
-extern struct clk_ops tegra_clk_32k_ops;
+extern struct clk_ops tegra30_clk_32k_ops;
 extern struct clk_ops tegra30_clk_m_ops;
 extern struct clk_ops tegra_clk_m_div_ops;
 extern struct clk_ops tegra_pll_ref_ops;

diff --git a/trunk/arch/arm/mach-tegra/tegra30_clocks_data.c b/trunk/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -57,7 +57,7 @@ static struct clk_tegra tegra_clk_32k_hw = {
 static struct clk tegra_clk_32k = {
 	.name = "clk_32k",
 	.hw = &tegra_clk_32k_hw.hw,
-	.ops = &tegra_clk_32k_ops,
+	.ops = &tegra30_clk_32k_ops,
 	.flags = CLK_IS_ROOT,
 };