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pinctrl: sirf: move sgpio lock into state container
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Instead of referring to a global static variable for the sgpio
locking, use the state container to contain the lock.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Linus Walleij committed Apr 9, 2015
1 parent 7414b09 commit 1dfe0d1
Showing 1 changed file with 12 additions and 12 deletions.
24 changes: 12 additions & 12 deletions drivers/pinctrl/sirf/pinctrl-sirf.c
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Original file line number Diff line number Diff line change
Expand Up @@ -39,10 +39,9 @@ struct sirfsoc_gpio_bank {
struct sirfsoc_gpio_chip {
struct of_mm_gpio_chip chip;
struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
spinlock_t lock;
};

static DEFINE_SPINLOCK(sgpio_lock);

static struct sirfsoc_pin_group *sirfsoc_pin_groups;
static int sirfsoc_pingrp_cnt;

Expand Down Expand Up @@ -427,13 +426,13 @@ static void sirfsoc_gpio_irq_ack(struct irq_data *d)

offset = SIRFSOC_GPIO_CTRL(bank->id, idx);

spin_lock_irqsave(&sgpio_lock, flags);
spin_lock_irqsave(&sgpio->lock, flags);

val = readl(sgpio->chip.regs + offset);

writel(val, sgpio->chip.regs + offset);

spin_unlock_irqrestore(&sgpio_lock, flags);
spin_unlock_irqrestore(&sgpio->lock, flags);
}

static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio,
Expand All @@ -445,14 +444,14 @@ static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio,

offset = SIRFSOC_GPIO_CTRL(bank->id, idx);

spin_lock_irqsave(&sgpio_lock, flags);
spin_lock_irqsave(&sgpio->lock, flags);

val = readl(sgpio->chip.regs + offset);
val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
writel(val, sgpio->chip.regs + offset);

spin_unlock_irqrestore(&sgpio_lock, flags);
spin_unlock_irqrestore(&sgpio->lock, flags);
}

static void sirfsoc_gpio_irq_mask(struct irq_data *d)
Expand All @@ -475,14 +474,14 @@ static void sirfsoc_gpio_irq_unmask(struct irq_data *d)

offset = SIRFSOC_GPIO_CTRL(bank->id, idx);

spin_lock_irqsave(&sgpio_lock, flags);
spin_lock_irqsave(&sgpio->lock, flags);

val = readl(sgpio->chip.regs + offset);
val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
writel(val, sgpio->chip.regs + offset);

spin_unlock_irqrestore(&sgpio_lock, flags);
spin_unlock_irqrestore(&sgpio->lock, flags);
}

static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
Expand All @@ -496,7 +495,7 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)

offset = SIRFSOC_GPIO_CTRL(bank->id, idx);

spin_lock_irqsave(&sgpio_lock, flags);
spin_lock_irqsave(&sgpio->lock, flags);

val = readl(sgpio->chip.regs + offset);
val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK);
Expand Down Expand Up @@ -533,7 +532,7 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)

writel(val, sgpio->chip.regs + offset);

spin_unlock_irqrestore(&sgpio_lock, flags);
spin_unlock_irqrestore(&sgpio->lock, flags);

return 0;
}
Expand Down Expand Up @@ -697,11 +696,11 @@ static int sirfsoc_gpio_direction_output(struct gpio_chip *chip,

offset = SIRFSOC_GPIO_CTRL(bank->id, idx);

spin_lock_irqsave(&sgpio_lock, flags);
spin_lock_irqsave(&sgpio->lock, flags);

sirfsoc_gpio_set_output(sgpio, bank, offset, value);

spin_unlock_irqrestore(&sgpio_lock, flags);
spin_unlock_irqrestore(&sgpio->lock, flags);

return 0;
}
Expand Down Expand Up @@ -793,6 +792,7 @@ static int sirfsoc_gpio_probe(struct device_node *np)
sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL);
if (!sgpio)
return -ENOMEM;
spin_lock_init(&sgpio->lock);

regs = of_iomap(np, 0);
if (!regs)
Expand Down

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