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yaml
---
r: 372125
b: refs/heads/master
c: ae8a8b9
h: refs/heads/master
i:
  372123: b006571
v: v3
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Will Deacon authored and Russell King committed Apr 3, 2013
1 parent b756db3 commit 1e2d8ec
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Showing 6 changed files with 8 additions and 8 deletions.
2 changes: 1 addition & 1 deletion [refs]
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@@ -1,2 +1,2 @@
---
refs/heads/master: b00884802043d9102ecc2abfdc37a7b35b30e52a
refs/heads/master: ae8a8b9553bd3906af74ff4e8d763904d20ab4e5
2 changes: 1 addition & 1 deletion trunk/arch/arm/include/asm/tlbflush.h
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Expand Up @@ -169,7 +169,7 @@
# define v6wbi_always_flags (-1UL)
#endif

#define v7wbi_tlb_flags_smp (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
#define v7wbi_tlb_flags_smp (TLB_WB | TLB_BARRIER | \
TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | \
TLB_V7_UIS_ASID | TLB_V7_UIS_BP)
#define v7wbi_tlb_flags_up (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
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2 changes: 0 additions & 2 deletions trunk/arch/arm/mm/proc-v6.S
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Expand Up @@ -80,12 +80,10 @@ ENTRY(cpu_v6_do_idle)
mov pc, lr

ENTRY(cpu_v6_dcache_clean_area)
#ifndef TLB_CAN_READ_FROM_L1_CACHE
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
add r0, r0, #D_CACHE_LINE_SIZE
subs r1, r1, #D_CACHE_LINE_SIZE
bhi 1b
#endif
mov pc, lr

/*
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3 changes: 2 additions & 1 deletion trunk/arch/arm/mm/proc-v7-2level.S
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Expand Up @@ -110,7 +110,8 @@ ENTRY(cpu_v7_set_pte_ext)
ARM( str r3, [r0, #2048]! )
THUMB( add r0, r0, #2048 )
THUMB( str r3, [r0] )
mcr p15, 0, r0, c7, c10, 1 @ flush_pte
ALT_SMP(mov pc,lr)
ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte
#endif
mov pc, lr
ENDPROC(cpu_v7_set_pte_ext)
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3 changes: 2 additions & 1 deletion trunk/arch/arm/mm/proc-v7-3level.S
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Expand Up @@ -73,7 +73,8 @@ ENTRY(cpu_v7_set_pte_ext)
tst r3, #1 << (55 - 32) @ L_PTE_DIRTY
orreq r2, #L_PTE_RDONLY
1: strd r2, r3, [r0]
mcr p15, 0, r0, c7, c10, 1 @ flush_pte
ALT_SMP(mov pc, lr)
ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte
#endif
mov pc, lr
ENDPROC(cpu_v7_set_pte_ext)
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4 changes: 2 additions & 2 deletions trunk/arch/arm/mm/proc-v7.S
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Expand Up @@ -75,14 +75,14 @@ ENTRY(cpu_v7_do_idle)
ENDPROC(cpu_v7_do_idle)

ENTRY(cpu_v7_dcache_clean_area)
#ifndef TLB_CAN_READ_FROM_L1_CACHE
ALT_SMP(mov pc, lr) @ MP extensions imply L1 PTW
ALT_UP(W(nop))
dcache_line_size r2, r3
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
add r0, r0, r2
subs r1, r1, r2
bhi 1b
dsb
#endif
mov pc, lr
ENDPROC(cpu_v7_dcache_clean_area)

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