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yaml
---
r: 279901
b: refs/heads/master
c: d675d0b
h: refs/heads/master
i:
  279899: 8d9ddf3
v: v3
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Will Deacon authored and Catalin Marinas committed Dec 8, 2011
1 parent 6b7b9c0 commit 20d2e59
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Showing 5 changed files with 17 additions and 1 deletion.
2 changes: 1 addition & 1 deletion [refs]
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@@ -1,2 +1,2 @@
---
refs/heads/master: 8d2cd3a38fd663bd341507f5ac29002ffd81d986
refs/heads/master: d675d0bc47f28c5414fbbe17fcc801f69c45b960
1 change: 1 addition & 0 deletions trunk/arch/arm/boot/compressed/head.S
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Expand Up @@ -659,6 +659,7 @@ __armv7_mmu_cache_on:
mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
#endif
mcr p15, 0, r0, c7, c5, 4 @ ISB
mcr p15, 0, r0, c1, c0, 0 @ load control register
mrc p15, 0, r0, c1, c0, 0 @ and read it back
mov r0, #0
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11 changes: 11 additions & 0 deletions trunk/arch/arm/include/asm/assembler.h
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Expand Up @@ -186,6 +186,17 @@
#define ALT_UP_B(label) b label
#endif

/*
* Instruction barrier
*/
.macro instr_sync
#if __LINUX_ARM_ARCH__ >= 7
isb
#elif __LINUX_ARM_ARCH__ == 6
mcr p15, 0, r0, c7, c5, 4
#endif
.endm

/*
* SMP data memory barrier
*/
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2 changes: 2 additions & 0 deletions trunk/arch/arm/kernel/head.S
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Expand Up @@ -401,8 +401,10 @@ ENDPROC(__enable_mmu)
.pushsection .idmap.text, "ax"
ENTRY(__turn_mmu_on)
mov r0, r0
instr_sync
mcr p15, 0, r0, c1, c0, 0 @ write control reg
mrc p15, 0, r3, c0, c0, 0 @ read id reg
instr_sync
mov r3, r3
mov r3, r13
mov pc, r3
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2 changes: 2 additions & 0 deletions trunk/arch/arm/kernel/sleep.S
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Expand Up @@ -57,8 +57,10 @@ ENDPROC(cpu_suspend_abort)
.pushsection .idmap.text,"ax"
ENTRY(cpu_resume_mmu)
ldr r3, =cpu_resume_after_mmu
instr_sync
mcr p15, 0, r0, c1, c0, 0 @ turn on MMU, I-cache, etc
mrc p15, 0, r0, c0, c0, 0 @ read id reg
instr_sync
mov r0, r0
mov r0, r0
mov pc, r3 @ jump to virtual address
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