ARM: dt: tegra seaboard: fix I2C2 SCL rate

This I2C bus is used for EDID/DDC reads and other "slow" I2C devices. This requires a 100KHz SCL (clock) rate. Signed-off-by: Stephen Warren <swarren@nvidia.com>
git-mirror · May 3, 2012 · 22bd1f7 · 22bd1f7
1 parent b46b0b5
commit 22bd1f7
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -281,7 +281,7 @@
 	};
 
 	i2c@7000c400 {
-		clock-frequency = <400000>;
+		clock-frequency = <100000>;
 	};
 
 	i2c@7000c500 {