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yaml
---
r: 196201
b: refs/heads/master
c: d74b494
h: refs/heads/master
i:
  196199: 9d01243
v: v3
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Paul Walmsley committed May 20, 2010
1 parent 6252bd9 commit 22cef24
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Showing 7 changed files with 136 additions and 116 deletions.
2 changes: 1 addition & 1 deletion [refs]
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Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 275f675c24a16ea45cc78bc03ff73fd06be8bffb
refs/heads/master: d74b4949714741f4c58cd1801a6a92737b89a61c
57 changes: 39 additions & 18 deletions trunk/arch/arm/mach-omap2/clkt_clksel.c
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Original file line number Diff line number Diff line change
Expand Up @@ -67,38 +67,61 @@ static const struct clksel *_omap2_get_clksel_by_parent(struct clk *clk,
return clks;
}

/*
* Converts encoded control register address into a full address
* On error, the return value (parent_div) will be 0.
/**
* _omap2_clksel_get_src_field - find the new clksel divisor to use
* @src_clk: planned new parent struct clk *
* @clk: struct clk * that is being reparented
* @field_val: pointer to a u32 to contain the register data for the divisor
*
* Given an intended new parent struct clk * @src_clk, and the struct
* clk * @clk to the clock that is being reparented, find the
* appropriate rate divisor for the new clock (returned as the return
* value), and the corresponding register bitfield data to program to
* reach that divisor (returned in the u32 pointed to by @field_val).
* Returns 0 on error, or returns the newly-selected divisor upon
* success (in this latter case, the corresponding register bitfield
* value is passed back in the variable pointed to by @field_val)
*/
static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk,
u32 *field_val)
static u8 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk,
u32 *field_val)
{
const struct clksel *clks;
const struct clksel_rate *clkr;
const struct clksel_rate *clkr, *max_clkr;
u8 max_div = 0;

clks = _omap2_get_clksel_by_parent(clk, src_clk);
if (!clks)
return 0;

/*
* Find the highest divisor (e.g., the one resulting in the
* lowest rate) to use as the default. This should avoid
* clock rates that are too high for the device. XXX A better
* solution here would be to try to determine if there is a
* divisor matching the original clock rate before the parent
* switch, and if it cannot be found, to fall back to the
* highest divisor.
*/
for (clkr = clks->rates; clkr->div; clkr++) {
if (clkr->flags & cpu_mask && clkr->flags & DEFAULT_RATE)
break; /* Found the default rate for this platform */
if (!(clkr->flags & cpu_mask))
continue;

if (clkr->div > max_div) {
max_div = clkr->div;
max_clkr = clkr;
}
}

if (!clkr->div) {
printk(KERN_ERR "clock: Could not find default rate for "
if (max_div == 0) {
WARN(1, "clock: Could not find divisor for "
"clock %s parent %s\n", clk->name,
src_clk->parent->name);
return 0;
}

/* Should never happen. Add a clksel mask to the struct clk. */
WARN_ON(clk->clksel_mask == 0);
*field_val = max_clkr->val;

*field_val = clkr->val;

return clkr->div;
return max_div;
}


Expand Down Expand Up @@ -177,8 +200,6 @@ unsigned long omap2_clksel_recalc(struct clk *clk)
*
* Finds 'best' divider value in an array based on the source and target
* rates. The divider array must be sorted with smallest divider first.
* Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
* they are only settable as part of virtual_prcm set.
*
* Returns the rounded clock rate or returns 0xffffffff on error.
*/
Expand Down Expand Up @@ -380,7 +401,7 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
{
u32 field_val, v, parent_div;

if (!clk->clksel)
if (!clk->clksel || !clk->clksel_mask)
return -EINVAL;

parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val);
Expand Down
46 changes: 23 additions & 23 deletions trunk/arch/arm/mach-omap2/clock2420_data.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -155,12 +155,12 @@ static struct clk apll54_ck = {
/* func_54m_ck */

static const struct clksel_rate func_54m_apll54_rates[] = {
{ .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
{ .div = 1, .val = 0, .flags = RATE_IN_24XX },
{ .div = 0 },
};

static const struct clksel_rate func_54m_alt_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
{ .div = 0 },
};

Expand Down Expand Up @@ -201,12 +201,12 @@ static struct clk func_96m_ck = {
/* func_48m_ck */

static const struct clksel_rate func_48m_apll96_rates[] = {
{ .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
{ .div = 2, .val = 0, .flags = RATE_IN_24XX },
{ .div = 0 },
};

static const struct clksel_rate func_48m_alt_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
{ .div = 0 },
};

Expand Down Expand Up @@ -256,22 +256,22 @@ static struct clk wdt1_osc_ck = {
* flags fields, which mark them as 2420-only.
*/
static const struct clksel_rate common_clkout_src_core_rates[] = {
{ .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
{ .div = 1, .val = 0, .flags = RATE_IN_24XX },
{ .div = 0 }
};

static const struct clksel_rate common_clkout_src_sys_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
{ .div = 0 }
};

static const struct clksel_rate common_clkout_src_96m_rates[] = {
{ .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
{ .div = 1, .val = 2, .flags = RATE_IN_24XX },
{ .div = 0 }
};

static const struct clksel_rate common_clkout_src_54m_rates[] = {
{ .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
{ .div = 1, .val = 3, .flags = RATE_IN_24XX },
{ .div = 0 }
};

Expand Down Expand Up @@ -300,7 +300,7 @@ static struct clk sys_clkout_src = {
};

static const struct clksel_rate common_clkout_rates[] = {
{ .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
{ .div = 1, .val = 0, .flags = RATE_IN_24XX },
{ .div = 2, .val = 1, .flags = RATE_IN_24XX },
{ .div = 4, .val = 2, .flags = RATE_IN_24XX },
{ .div = 8, .val = 3, .flags = RATE_IN_24XX },
Expand Down Expand Up @@ -384,7 +384,7 @@ static struct clk emul_ck = {
*
*/
static const struct clksel_rate mpu_core_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
{ .div = 4, .val = 4, .flags = RATE_IN_242X },
{ .div = 6, .val = 6, .flags = RATE_IN_242X },
Expand Down Expand Up @@ -420,7 +420,7 @@ static struct clk mpu_ck = { /* Control cpu */
* routed into a synchronizer and out of clocks abc.
*/
static const struct clksel_rate dsp_fck_core_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
{ .div = 3, .val = 3, .flags = RATE_IN_24XX },
{ .div = 4, .val = 4, .flags = RATE_IN_24XX },
Expand Down Expand Up @@ -450,7 +450,7 @@ static struct clk dsp_fck = {

/* DSP interface clock */
static const struct clksel_rate dsp_irate_ick_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
{ .div = 0 },
};
Expand Down Expand Up @@ -532,7 +532,7 @@ static struct clk iva1_mpu_int_ifck = {
static const struct clksel_rate core_l3_core_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
{ .div = 2, .val = 2, .flags = RATE_IN_242X },
{ .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
{ .div = 4, .val = 4, .flags = RATE_IN_24XX },
{ .div = 6, .val = 6, .flags = RATE_IN_24XX },
{ .div = 8, .val = 8, .flags = RATE_IN_242X },
{ .div = 12, .val = 12, .flags = RATE_IN_242X },
Expand All @@ -559,7 +559,7 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
/* usb_l4_ick */
static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
{ .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
{ .div = 4, .val = 4, .flags = RATE_IN_24XX },
{ .div = 0 }
};
Expand Down Expand Up @@ -591,7 +591,7 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */
* this domain.
*/
static const struct clksel_rate l4_core_l3_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
{ .div = 0 }
};
Expand Down Expand Up @@ -622,7 +622,7 @@ static struct clk l4_ck = { /* used both as an ick and fck */
*/
static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
{ .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
{ .div = 3, .val = 3, .flags = RATE_IN_24XX },
{ .div = 4, .val = 4, .flags = RATE_IN_24XX },
{ .div = 6, .val = 6, .flags = RATE_IN_242X },
Expand Down Expand Up @@ -730,7 +730,7 @@ static struct clk gfx_ick = {
/* XXX Add RATE_NOT_VALIDATED */

static const struct clksel_rate dss1_fck_sys_rates[] = {
{ .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
{ .div = 1, .val = 0, .flags = RATE_IN_24XX },
{ .div = 0 }
};

Expand All @@ -744,7 +744,7 @@ static const struct clksel_rate dss1_fck_core_rates[] = {
{ .div = 8, .val = 8, .flags = RATE_IN_24XX },
{ .div = 9, .val = 9, .flags = RATE_IN_24XX },
{ .div = 12, .val = 12, .flags = RATE_IN_24XX },
{ .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
{ .div = 16, .val = 16, .flags = RATE_IN_24XX },
{ .div = 0 }
};

Expand Down Expand Up @@ -779,12 +779,12 @@ static struct clk dss1_fck = {
};

static const struct clksel_rate dss2_fck_sys_rates[] = {
{ .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
{ .div = 1, .val = 0, .flags = RATE_IN_24XX },
{ .div = 0 }
};

static const struct clksel_rate dss2_fck_48m_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
{ .div = 0 }
};

Expand Down Expand Up @@ -825,7 +825,7 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */
* functional clock parents.
*/
static const struct clksel_rate gpt_alt_rates[] = {
{ .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
{ .div = 1, .val = 2, .flags = RATE_IN_24XX },
{ .div = 0 }
};

Expand Down Expand Up @@ -1588,7 +1588,7 @@ static struct clk vlynq_ick = {
};

static const struct clksel_rate vlynq_fck_96m_rates[] = {
{ .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
{ .div = 1, .val = 0, .flags = RATE_IN_242X },
{ .div = 0 }
};

Expand All @@ -1601,7 +1601,7 @@ static const struct clksel_rate vlynq_fck_core_rates[] = {
{ .div = 8, .val = 8, .flags = RATE_IN_242X },
{ .div = 9, .val = 9, .flags = RATE_IN_242X },
{ .div = 12, .val = 12, .flags = RATE_IN_242X },
{ .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
{ .div = 16, .val = 16, .flags = RATE_IN_242X },
{ .div = 18, .val = 18, .flags = RATE_IN_242X },
{ .div = 0 }
};
Expand Down
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