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yaml
---
r: 264208
b: refs/heads/master
c: 5bd078d
h: refs/heads/master
v: v3
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Rob Herring authored and Thomas Gleixner committed Sep 20, 2011
1 parent 4dd2158 commit 2310c9d
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2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 47ea91b4052d9e94b9dca5d7a3d947fbebd07ba9
refs/heads/master: 5bd078dda4d4fbdb4bd138a6bd5b6e274c019ed2
14 changes: 10 additions & 4 deletions trunk/Documentation/hwmon/coretemp
Original file line number Diff line number Diff line change
Expand Up @@ -35,17 +35,23 @@ the Out-Of-Spec bit. Following table summarizes the exported sysfs files:
All Sysfs entries are named with their core_id (represented here by 'X').
tempX_input - Core temperature (in millidegrees Celsius).
tempX_max - All cooling devices should be turned on (on Core2).
Initialized with IA32_THERM_INTERRUPT. When the CPU
temperature reaches this temperature, an interrupt is
generated and tempX_max_alarm is set.
tempX_max_hyst - If the CPU temperature falls below than temperature,
an interrupt is generated and tempX_max_alarm is reset.
tempX_max_alarm - Set if the temperature reaches or exceeds tempX_max.
Reset if the temperature drops to or below tempX_max_hyst.
tempX_crit - Maximum junction temperature (in millidegrees Celsius).
tempX_crit_alarm - Set when Out-of-spec bit is set, never clears.
Correct CPU operation is no longer guaranteed.
tempX_label - Contains string "Core X", where X is processor
number. For Package temp, this will be "Physical id Y",
where Y is the package number.

On CPU models which support it, TjMax is read from a model-specific register.
On other models, it is set to an arbitrary value based on weak heuristics.
If these heuristics don't work for you, you can pass the correct TjMax value
as a module parameter (tjmax).
The TjMax temperature is set to 85 degrees C if undocumented model specific
register (UMSR) 0xee has bit 30 set. If not the TjMax is 100 degrees C as
(sometimes) documented in processor datasheet.

Appendix A. Known TjMax lists (TBD):
Some information comes from ark.intel.com
Expand Down
2 changes: 1 addition & 1 deletion trunk/Documentation/networking/scaling.txt
Original file line number Diff line number Diff line change
Expand Up @@ -243,7 +243,7 @@ configured. The number of entries in the global flow table is set through:

The number of entries in the per-queue flow table are set through:

/sys/class/net/<dev>/queues/rx-<n>/rps_flow_cnt
/sys/class/net/<dev>/queues/tx-<n>/rps_flow_cnt

== Suggested Configuration

Expand Down
7 changes: 3 additions & 4 deletions trunk/Documentation/vm/transhuge.txt
Original file line number Diff line number Diff line change
Expand Up @@ -123,11 +123,10 @@ be automatically shutdown if it's set to "never".
khugepaged runs usually at low frequency so while one may not want to
invoke defrag algorithms synchronously during the page faults, it
should be worth invoking defrag at least in khugepaged. However it's
also possible to disable defrag in khugepaged by writing 0 or enable
defrag in khugepaged by writing 1:
also possible to disable defrag in khugepaged:

echo 0 >/sys/kernel/mm/transparent_hugepage/khugepaged/defrag
echo 1 >/sys/kernel/mm/transparent_hugepage/khugepaged/defrag
echo yes >/sys/kernel/mm/transparent_hugepage/khugepaged/defrag
echo no >/sys/kernel/mm/transparent_hugepage/khugepaged/defrag

You can also control how many pages khugepaged should scan at each
pass:
Expand Down
2 changes: 1 addition & 1 deletion trunk/Makefile
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
VERSION = 3
PATCHLEVEL = 1
SUBLEVEL = 0
EXTRAVERSION = -rc8
EXTRAVERSION = -rc6
NAME = "Divemaster Edition"

# *DOCUMENTATION*
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14 changes: 0 additions & 14 deletions trunk/arch/arm/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -1283,20 +1283,6 @@ config ARM_ERRATA_364296
processor into full low interrupt latency mode. ARM11MPCore
is not affected.

config ARM_ERRATA_764369
bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
depends on CPU_V7 && SMP
help
This option enables the workaround for erratum 764369
affecting Cortex-A9 MPCore with two or more processors (all
current revisions). Under certain timing circumstances, a data
cache line maintenance operation by MVA targeting an Inner
Shareable memory region may fail to proceed up to either the
Point of Coherency or to the Point of Unification of the
system. This workaround adds a DSB instruction before the
relevant cache maintenance functions and sets a specific bit
in the diagnostic control register of the SCU.

endmenu

source "arch/arm/common/Kconfig"
Expand Down
12 changes: 6 additions & 6 deletions trunk/arch/arm/boot/dts/tegra-harmony.dts
Original file line number Diff line number Diff line change
Expand Up @@ -57,14 +57,14 @@
};

sdhci@c8000200 {
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
power-gpios = <&gpio 155 0>; /* gpio PT3 */
gpios = <&gpio 69 0>, /* cd, gpio PI5 */
<&gpio 57 0>, /* wp, gpio PH1 */
<&gpio 155 0>; /* power, gpio PT3 */
};

sdhci@c8000600 {
cd-gpios = <&gpio 58 0>; /* gpio PH2 */
wp-gpios = <&gpio 59 0>; /* gpio PH3 */
power-gpios = <&gpio 70 0>; /* gpio PI6 */
gpios = <&gpio 58 0>, /* cd, gpio PH2 */
<&gpio 59 0>, /* wp, gpio PH3 */
<&gpio 70 0>; /* power, gpio PI6 */
};
};
6 changes: 3 additions & 3 deletions trunk/arch/arm/boot/dts/tegra-seaboard.dts
Original file line number Diff line number Diff line change
Expand Up @@ -21,8 +21,8 @@
};

sdhci@c8000400 {
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
power-gpios = <&gpio 70 0>; /* gpio PI6 */
gpios = <&gpio 69 0>, /* cd, gpio PI5 */
<&gpio 57 0>, /* wp, gpio PH1 */
<&gpio 70 0>; /* power, gpio PI6 */
};
};
34 changes: 17 additions & 17 deletions trunk/arch/arm/include/asm/futex.h
Original file line number Diff line number Diff line change
Expand Up @@ -25,17 +25,17 @@

#ifdef CONFIG_SMP

#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
smp_mb(); \
__asm__ __volatile__( \
"1: ldrex %1, [%3]\n" \
"1: ldrex %1, [%2]\n" \
" " insn "\n" \
"2: strex %2, %0, [%3]\n" \
" teq %2, #0\n" \
"2: strex %1, %0, [%2]\n" \
" teq %1, #0\n" \
" bne 1b\n" \
" mov %0, #0\n" \
__futex_atomic_ex_table("%5") \
: "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
__futex_atomic_ex_table("%4") \
: "=&r" (ret), "=&r" (oldval) \
: "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
: "cc", "memory")

Expand Down Expand Up @@ -73,14 +73,14 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
#include <linux/preempt.h>
#include <asm/domain.h>

#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
__asm__ __volatile__( \
"1: " T(ldr) " %1, [%3]\n" \
"1: " T(ldr) " %1, [%2]\n" \
" " insn "\n" \
"2: " T(str) " %0, [%3]\n" \
"2: " T(str) " %0, [%2]\n" \
" mov %0, #0\n" \
__futex_atomic_ex_table("%5") \
: "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
__futex_atomic_ex_table("%4") \
: "=&r" (ret), "=&r" (oldval) \
: "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
: "cc", "memory")

Expand Down Expand Up @@ -117,7 +117,7 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
int cmp = (encoded_op >> 24) & 15;
int oparg = (encoded_op << 8) >> 20;
int cmparg = (encoded_op << 20) >> 20;
int oldval = 0, ret, tmp;
int oldval = 0, ret;

if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
oparg = 1 << oparg;
Expand All @@ -129,19 +129,19 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)

switch (op) {
case FUTEX_OP_SET:
__futex_atomic_op("mov %0, %4", ret, oldval, tmp, uaddr, oparg);
__futex_atomic_op("mov %0, %3", ret, oldval, uaddr, oparg);
break;
case FUTEX_OP_ADD:
__futex_atomic_op("add %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
__futex_atomic_op("add %0, %1, %3", ret, oldval, uaddr, oparg);
break;
case FUTEX_OP_OR:
__futex_atomic_op("orr %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
__futex_atomic_op("orr %0, %1, %3", ret, oldval, uaddr, oparg);
break;
case FUTEX_OP_ANDN:
__futex_atomic_op("and %0, %1, %4", ret, oldval, tmp, uaddr, ~oparg);
__futex_atomic_op("and %0, %1, %3", ret, oldval, uaddr, ~oparg);
break;
case FUTEX_OP_XOR:
__futex_atomic_op("eor %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
__futex_atomic_op("eor %0, %1, %3", ret, oldval, uaddr, oparg);
break;
default:
ret = -ENOSYS;
Expand Down
4 changes: 2 additions & 2 deletions trunk/arch/arm/include/asm/unistd.h
Original file line number Diff line number Diff line change
Expand Up @@ -478,8 +478,8 @@
/*
* Unimplemented (or alternatively implemented) syscalls
*/
#define __IGNORE_fadvise64_64
#define __IGNORE_migrate_pages
#define __IGNORE_fadvise64_64 1
#define __IGNORE_migrate_pages 1

#endif /* __KERNEL__ */
#endif /* __ASM_ARM_UNISTD_H */
10 changes: 0 additions & 10 deletions trunk/arch/arm/kernel/smp_scu.c
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,6 @@

#include <asm/smp_scu.h>
#include <asm/cacheflush.h>
#include <asm/cputype.h>

#define SCU_CTRL 0x00
#define SCU_CONFIG 0x04
Expand All @@ -38,15 +37,6 @@ void __init scu_enable(void __iomem *scu_base)
{
u32 scu_ctrl;

#ifdef CONFIG_ARM_ERRATA_764369
/* Cortex-A9 only */
if ((read_cpuid(CPUID_ID) & 0xff0ffff0) == 0x410fc090) {
scu_ctrl = __raw_readl(scu_base + 0x30);
if (!(scu_ctrl & 1))
__raw_writel(scu_ctrl | 0x1, scu_base + 0x30);
}
#endif

scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
/* already enabled? */
if (scu_ctrl & 1)
Expand Down
15 changes: 3 additions & 12 deletions trunk/arch/arm/kernel/vmlinux.lds.S
Original file line number Diff line number Diff line change
Expand Up @@ -23,10 +23,8 @@

#if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)
#define ARM_EXIT_KEEP(x) x
#define ARM_EXIT_DISCARD(x)
#else
#define ARM_EXIT_KEEP(x)
#define ARM_EXIT_DISCARD(x) x
#endif

OUTPUT_ARCH(arm)
Expand All @@ -41,11 +39,6 @@ jiffies = jiffies_64 + 4;
SECTIONS
{
/*
* XXX: The linker does not define how output sections are
* assigned to input sections when there are multiple statements
* matching the same input section name. There is no documented
* order of matching.
*
* unwind exit sections must be discarded before the rest of the
* unwind sections get included.
*/
Expand All @@ -54,9 +47,6 @@ SECTIONS
*(.ARM.extab.exit.text)
ARM_CPU_DISCARD(*(.ARM.exidx.cpuexit.text))
ARM_CPU_DISCARD(*(.ARM.extab.cpuexit.text))
ARM_EXIT_DISCARD(EXIT_TEXT)
ARM_EXIT_DISCARD(EXIT_DATA)
EXIT_CALL
#ifndef CONFIG_HOTPLUG
*(.ARM.exidx.devexit.text)
*(.ARM.extab.devexit.text)
Expand All @@ -68,8 +58,6 @@ SECTIONS
#ifndef CONFIG_SMP_ON_UP
*(.alt.smp.init)
#endif
*(.discard)
*(.discard.*)
}

#ifdef CONFIG_XIP_KERNEL
Expand Down Expand Up @@ -291,6 +279,9 @@ SECTIONS

STABS_DEBUG
.comment 0 : { *(.comment) }

/* Default discards */
DISCARDS
}

/*
Expand Down
2 changes: 1 addition & 1 deletion trunk/arch/arm/mach-dove/common.c
Original file line number Diff line number Diff line change
Expand Up @@ -158,7 +158,7 @@ void __init dove_spi0_init(void)

void __init dove_spi1_init(void)
{
orion_spi_1_init(DOVE_SPI1_PHYS_BASE, get_tclk());
orion_spi_init(DOVE_SPI1_PHYS_BASE, get_tclk());
}

/*****************************************************************************
Expand Down
8 changes: 5 additions & 3 deletions trunk/arch/arm/mach-exynos4/clock.c
Original file line number Diff line number Diff line change
Expand Up @@ -899,7 +899,8 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
}, {
.clk = {
.name = "sclk_cam0",
.name = "sclk_cam",
.devname = "exynos4-fimc.0",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 16),
},
Expand All @@ -908,7 +909,8 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
}, {
.clk = {
.name = "sclk_cam1",
.name = "sclk_cam",
.devname = "exynos4-fimc.1",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 20),
},
Expand Down Expand Up @@ -1158,7 +1160,7 @@ void __init_or_cpufreq exynos4_setup_clocks(void)

vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
__raw_readl(S5P_VPLL_CON1), pll_4650c);
__raw_readl(S5P_VPLL_CON1), pll_4650);

clk_fout_apll.ops = &exynos4_fout_apll_ops;
clk_fout_mpll.rate = mpll;
Expand Down
10 changes: 1 addition & 9 deletions trunk/arch/arm/mach-exynos4/mct.c
Original file line number Diff line number Diff line change
Expand Up @@ -132,18 +132,12 @@ static cycle_t exynos4_frc_read(struct clocksource *cs)
return ((cycle_t)hi << 32) | lo;
}

static void exynos4_frc_resume(struct clocksource *cs)
{
exynos4_mct_frc_start(0, 0);
}

struct clocksource mct_frc = {
.name = "mct-frc",
.rating = 400,
.read = exynos4_frc_read,
.mask = CLOCKSOURCE_MASK(64),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
.resume = exynos4_frc_resume,
};

static void __init exynos4_clocksource_init(void)
Expand Down Expand Up @@ -395,11 +389,9 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
}

/* Setup the local clock events for a CPU */
int __cpuinit local_timer_setup(struct clock_event_device *evt)
void __cpuinit local_timer_setup(struct clock_event_device *evt)
{
exynos4_mct_tick_init(evt);

return 0;
}

int local_timer_ack(void)
Expand Down
2 changes: 0 additions & 2 deletions trunk/arch/arm/mach-exynos4/platsmp.c
Original file line number Diff line number Diff line change
Expand Up @@ -106,8 +106,6 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
*/
spin_lock(&boot_lock);
spin_unlock(&boot_lock);

set_cpu_online(cpu, true);
}

int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
Expand Down
11 changes: 5 additions & 6 deletions trunk/arch/arm/mach-exynos4/setup-keypad.c
Original file line number Diff line number Diff line change
Expand Up @@ -19,16 +19,15 @@ void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)

if (rows > 8) {
/* Set all the necessary GPX2 pins: KP_ROW[0~7] */
s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), 8, S3C_GPIO_SFN(3),
S3C_GPIO_PULL_UP);
s3c_gpio_cfgrange_nopull(EXYNOS4_GPX2(0), 8, S3C_GPIO_SFN(3));

/* Set all the necessary GPX3 pins: KP_ROW[8~] */
s3c_gpio_cfgall_range(EXYNOS4_GPX3(0), (rows - 8),
S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
s3c_gpio_cfgrange_nopull(EXYNOS4_GPX3(0), (rows - 8),
S3C_GPIO_SFN(3));
} else {
/* Set all the necessary GPX2 pins: KP_ROW[x] */
s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), rows, S3C_GPIO_SFN(3),
S3C_GPIO_PULL_UP);
s3c_gpio_cfgrange_nopull(EXYNOS4_GPX2(0), rows,
S3C_GPIO_SFN(3));
}

/* Set all the necessary GPX1 pins to special-function 3: KP_COL[x] */
Expand Down
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