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ARM: OMAP3xxx: hwmod: Convert SHAM crypto device data to hwmod
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Convert the device data for the OMAP3 SHAM2 (SHA1/MD5) crypto IP
from explicit platform_data to hwmod.

CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
[paul@pwsan.com: updated to use per-SoC registration lists for GP-only hwmods;
 fixed lines causing sparse warnings]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Mark A. Greer authored and Paul Walmsley committed Mar 30, 2013
1 parent fa7807b commit 26f88e6
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Showing 3 changed files with 101 additions and 48 deletions.
1 change: 1 addition & 0 deletions arch/arm/mach-omap2/cclock3xxx_data.c
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Original file line number Diff line number Diff line change
Expand Up @@ -3473,6 +3473,7 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "gpt1_fck", &gpt1_fck),
CLK(NULL, "wkup_32k_fck", &wkup_32k_fck),
CLK(NULL, "gpio1_dbck", &gpio1_dbck),
CLK(NULL, "sha12_ick", &sha12_ick),
CLK(NULL, "wdt2_fck", &wdt2_fck),
CLK("omap_wdt", "ick", &wdt2_ick),
CLK(NULL, "wdt2_ick", &wdt2_ick),
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41 changes: 2 additions & 39 deletions arch/arm/mach-omap2/devices.c
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Original file line number Diff line number Diff line change
Expand Up @@ -504,38 +504,9 @@ static void omap_init_rng(void)
WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n");
}

#if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)

#ifdef CONFIG_ARCH_OMAP3
static struct resource omap3_sham_resources[] = {
{
.start = OMAP34XX_SEC_SHA1MD5_BASE,
.end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
.flags = IORESOURCE_MEM,
},
{
.start = 49 + OMAP_INTC_START,
.flags = IORESOURCE_IRQ,
},
{
.start = OMAP34XX_DMA_SHA1MD5_RX,
.flags = IORESOURCE_DMA,
}
};
static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
#else
#define omap3_sham_resources NULL
#define omap3_sham_resources_sz 0
#endif

static struct platform_device sham_device = {
.name = "omap-sham",
.id = -1,
};

static void omap_init_sham(void)
static void __init omap_init_sham(void)
{
if (cpu_is_omap24xx()) {
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
struct omap_hwmod *oh;
struct platform_device *pdev;

Expand All @@ -545,18 +516,10 @@ static void omap_init_sham(void)

pdev = omap_device_build("omap-sham", -1, oh, NULL, 0);
WARN(IS_ERR(pdev), "Can't build omap_device for omap-sham\n");
} else if (cpu_is_omap34xx()) {
sham_device.resource = omap3_sham_resources;
sham_device.num_resources = omap3_sham_resources_sz;
platform_device_register(&sham_device);
} else {
pr_err("%s: platform not supported\n", __func__);
return;
}
}
#else
static inline void omap_init_sham(void) { }
#endif

#if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)

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107 changes: 98 additions & 9 deletions arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
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Original file line number Diff line number Diff line change
Expand Up @@ -3545,6 +3545,71 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = {
.sidle_shift = 4,
.srst_shift = 1,
.autoidle_shift = 0,
};

static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
.rev_offs = 0x5c,
.sysc_offs = 0x60,
.syss_offs = 0x64,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.sysc_fields = &omap3_sham_sysc_fields,
};

static struct omap_hwmod_class omap3xxx_sham_class = {
.name = "sham",
.sysc = &omap3_sham_sysc,
};

static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = {
{ .irq = 49 + OMAP_INTC_START, },
{ .irq = -1 }
};

static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = {
{ .name = "rx", .dma_req = OMAP34XX_DMA_SHA1MD5_RX, },
{ .dma_req = -1 }
};

static struct omap_hwmod omap3xxx_sham_hwmod = {
.name = "sham",
.mpu_irqs = omap3_sham_mpu_irqs,
.sdma_reqs = omap3_sham_sdma_reqs,
.main_clk = "sha12_ick",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
.prcm_reg_id = 1,
.module_bit = OMAP3430_EN_SHA12_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
},
},
.class = &omap3xxx_sham_class,
};

static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = {
{
.pa_start = 0x480c3000,
.pa_end = 0x480c3000 + 0x64 - 1,
.flags = ADDR_TYPE_RT
},
{ }
};

static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_sham_hwmod,
.clk = "sha12_ick",
.addr = omap3xxx_sham_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l3_main__l4_core,
&omap3xxx_l3_main__l4_per,
Expand Down Expand Up @@ -3596,8 +3661,28 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
};

/* GP-only hwmod links */
static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_sec__timer12,
&omap3xxx_l4_core__sham,
NULL
};

static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_sec__timer12,
&omap3xxx_l4_core__sham,
NULL
};

static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_sec__timer12,
/*
* Apparently the SHA/MD5 accelerator IP block is only present
* on some AM35xx chips, and no one knows which ones. See
* http://www.spinics.net/lists/arm-kernel/msg215466.html So
* if you need this IP block on an AM35xx, try uncommenting
* the next line.
*/
/* &omap3xxx_l4_core__sham, */
NULL
};

Expand Down Expand Up @@ -3704,7 +3789,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
int __init omap3xxx_hwmod_init(void)
{
int r;
struct omap_hwmod_ocp_if **h = NULL;
struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL;
unsigned int rev;

omap_hwmod_init();
Expand All @@ -3714,13 +3799,6 @@ int __init omap3xxx_hwmod_init(void)
if (r < 0)
return r;

/* Register GP-only hwmod links. */
if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
if (r < 0)
return r;
}

rev = omap_rev();

/*
Expand All @@ -3732,11 +3810,14 @@ int __init omap3xxx_hwmod_init(void)
rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
h = omap34xx_hwmod_ocp_ifs;
h_gp = omap34xx_gp_hwmod_ocp_ifs;
} else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
h = am35xx_hwmod_ocp_ifs;
h_gp = am35xx_gp_hwmod_ocp_ifs;
} else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
rev == OMAP3630_REV_ES1_2) {
h = omap36xx_hwmod_ocp_ifs;
h_gp = omap36xx_gp_hwmod_ocp_ifs;
} else {
WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
return -EINVAL;
Expand All @@ -3746,6 +3827,14 @@ int __init omap3xxx_hwmod_init(void)
if (r < 0)
return r;

/* Register GP-only hwmod links. */
if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
r = omap_hwmod_register_links(h_gp);
if (r < 0)
return r;
}


/*
* Register hwmod links specific to certain ES levels of a
* particular family of silicon (e.g., 34xx ES1.0)
Expand Down

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