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yaml
---
r: 143865
b: refs/heads/master
c: f92ef20
h: refs/heads/master
i:
  143863: 91ee3f6
v: v3
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PJ Waskiewicz authored and David S. Miller committed Apr 17, 2009
1 parent 6c485c1 commit 27e4bc8
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Showing 2 changed files with 49 additions and 5 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 843f42678f6c47a2c8d1648e584cb57ebff3750f
refs/heads/master: f92ef202988ffb07bb86cf94d0b09f2a61192da7
52 changes: 48 additions & 4 deletions trunk/drivers/net/ixgbe/ixgbe_main.c
Original file line number Diff line number Diff line change
Expand Up @@ -2841,11 +2841,55 @@ static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
}
ret = true;
} else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
for (i = 0; i < dcb_i; i++) {
adapter->rx_ring[i].reg_idx = i << 4;
adapter->tx_ring[i].reg_idx = i << 4;
if (dcb_i == 8) {
/*
* Tx TC0 starts at: descriptor queue 0
* Tx TC1 starts at: descriptor queue 32
* Tx TC2 starts at: descriptor queue 64
* Tx TC3 starts at: descriptor queue 80
* Tx TC4 starts at: descriptor queue 96
* Tx TC5 starts at: descriptor queue 104
* Tx TC6 starts at: descriptor queue 112
* Tx TC7 starts at: descriptor queue 120
*
* Rx TC0-TC7 are offset by 16 queues each
*/
for (i = 0; i < 3; i++) {
adapter->tx_ring[i].reg_idx = i << 5;
adapter->rx_ring[i].reg_idx = i << 4;
}
for ( ; i < 5; i++) {
adapter->tx_ring[i].reg_idx =
((i + 2) << 4);
adapter->rx_ring[i].reg_idx = i << 4;
}
for ( ; i < dcb_i; i++) {
adapter->tx_ring[i].reg_idx =
((i + 8) << 3);
adapter->rx_ring[i].reg_idx = i << 4;
}

ret = true;
} else if (dcb_i == 4) {
/*
* Tx TC0 starts at: descriptor queue 0
* Tx TC1 starts at: descriptor queue 64
* Tx TC2 starts at: descriptor queue 96
* Tx TC3 starts at: descriptor queue 112
*
* Rx TC0-TC3 are offset by 32 queues each
*/
adapter->tx_ring[0].reg_idx = 0;
adapter->tx_ring[1].reg_idx = 64;
adapter->tx_ring[2].reg_idx = 96;
adapter->tx_ring[3].reg_idx = 112;
for (i = 0 ; i < dcb_i; i++)
adapter->rx_ring[i].reg_idx = i << 5;

ret = true;
} else {
ret = false;
}
ret = true;
} else {
ret = false;
}
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