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Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/…
…arm-soc Pull "ARM: SoC specific updates" from Arnd Bergmann: "These changes are all specific to an soc family or the code for one soc. Lots of work for Tegra3 this time, but also a lot of other platforms. There will be another (smaller) set of soc patches later in the merge window for stuff that has dependencies on external trees or that was sent just before the merge window opened. The asoc tree added a few devices to the i.mx platform, which conflict with other devices added in the same place here. The tegra Makefile conflicts between a number of branches, mostly because of changes regarding localtimer.c, which was removed in the end. Signed-off-by: Arnd Bergmann <arnd@arndb.de>" Fix up some trivial conflicts, including the mentioned Tegra Makefile. * tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (51 commits) ARM: EXYNOS: fix cycle count for periodic mode of clock event timers ARM: EXYNOS: add support JPEG ARM: EXYNOS: Add DMC1, allow PPMU access for DMC ARM: SAMSUNG: Correct MIPI-CSIS io memory resource definition ARM: SAMSUNG: fix __init attribute on regarding s3c_set_platdata() ARM: SAMSUNG: Add __init attribute to samsung_bl_set() ARM: S5PV210: Add usb otg phy control ARM: S3C64XX: Add usb otg phy control ARM: EXYNOS: Enable l2 configuration through device tree ARM: EXYNOS: remove useless code to save/restore L2 ARM: EXYNOS: save L2 settings during bootup ARM: S5P: add L2 early resume code ARM: EXYNOS: Add support AFTR mode on EXYNOS4210 ARM: mx35: Setup the AIPS registers ARM: mx5: Use common function for configuring AIPS ARM: mx3: Setup AIPS registers ARM: mx3: Let mx31 and mx35 enter in LPM mode in WFI ARM: defconfig: imx_v6_v7: build in REGULATOR_FIXED_VOLTAGE ARM: imx: update imx_v6_v7_defconfig ARM: tegra: Demote EMC clock inconsistency BUG to WARN ...
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,37 @@ | ||
| /* | ||
| * at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board | ||
| * | ||
| * Copyright (C) 2012 Atmel, | ||
| * 2012 Nicolas Ferre <nicolas.ferre@atmel.com> | ||
| * | ||
| * Licensed under GPLv2 or later. | ||
| */ | ||
| /dts-v1/; | ||
| /include/ "at91sam9x5.dtsi" | ||
| /include/ "at91sam9x5cm.dtsi" | ||
|
|
||
| / { | ||
| model = "Atmel AT91SAM9G25-EK"; | ||
| compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; | ||
|
|
||
| chosen { | ||
| bootargs = "128M console=ttyS0,115200 mtdparts=atmel_nand:8M(bootstrap/uboot/kernel)ro,-(rootfs) root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs"; | ||
| }; | ||
|
|
||
| ahb { | ||
| apb { | ||
| dbgu: serial@fffff200 { | ||
| status = "okay"; | ||
| }; | ||
|
|
||
| usart0: serial@f801c000 { | ||
| status = "okay"; | ||
| }; | ||
|
|
||
| macb0: ethernet@f802c000 { | ||
| phy-mode = "rmii"; | ||
| status = "okay"; | ||
| }; | ||
| }; | ||
| }; | ||
| }; |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,172 @@ | ||
| /* | ||
| * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC | ||
| * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, | ||
| * AT91SAM9X25, AT91SAM9X35 SoC | ||
| * | ||
| * Copyright (C) 2012 Atmel, | ||
| * 2012 Nicolas Ferre <nicolas.ferre@atmel.com> | ||
| * | ||
| * Licensed under GPLv2 or later. | ||
| */ | ||
|
|
||
| /include/ "skeleton.dtsi" | ||
|
|
||
| / { | ||
| model = "Atmel AT91SAM9x5 family SoC"; | ||
| compatible = "atmel,at91sam9x5"; | ||
| interrupt-parent = <&aic>; | ||
|
|
||
| aliases { | ||
| serial0 = &dbgu; | ||
| serial1 = &usart0; | ||
| serial2 = &usart1; | ||
| serial3 = &usart2; | ||
| gpio0 = &pioA; | ||
| gpio1 = &pioB; | ||
| gpio2 = &pioC; | ||
| gpio3 = &pioD; | ||
| tcb0 = &tcb0; | ||
| tcb1 = &tcb1; | ||
| }; | ||
| cpus { | ||
| cpu@0 { | ||
| compatible = "arm,arm926ejs"; | ||
| }; | ||
| }; | ||
|
|
||
| memory@20000000 { | ||
| reg = <0x20000000 0x10000000>; | ||
| }; | ||
|
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||
| ahb { | ||
| compatible = "simple-bus"; | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
| ranges; | ||
|
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||
| apb { | ||
| compatible = "simple-bus"; | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
| ranges; | ||
|
|
||
| aic: interrupt-controller@fffff000 { | ||
| #interrupt-cells = <2>; | ||
| compatible = "atmel,at91rm9200-aic"; | ||
| interrupt-controller; | ||
| interrupt-parent; | ||
| reg = <0xfffff000 0x200>; | ||
| }; | ||
|
|
||
| pit: timer@fffffe30 { | ||
| compatible = "atmel,at91sam9260-pit"; | ||
| reg = <0xfffffe30 0xf>; | ||
| interrupts = <1 4>; | ||
| }; | ||
|
|
||
| tcb0: timer@f8008000 { | ||
| compatible = "atmel,at91sam9x5-tcb"; | ||
| reg = <0xf8008000 0x100>; | ||
| interrupts = <17 4>; | ||
| }; | ||
|
|
||
| tcb1: timer@f800c000 { | ||
| compatible = "atmel,at91sam9x5-tcb"; | ||
| reg = <0xf800c000 0x100>; | ||
| interrupts = <17 4>; | ||
| }; | ||
|
|
||
| dma0: dma-controller@ffffec00 { | ||
| compatible = "atmel,at91sam9g45-dma"; | ||
| reg = <0xffffec00 0x200>; | ||
| interrupts = <20 4>; | ||
| }; | ||
|
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||
| dma1: dma-controller@ffffee00 { | ||
| compatible = "atmel,at91sam9g45-dma"; | ||
| reg = <0xffffee00 0x200>; | ||
| interrupts = <21 4>; | ||
| }; | ||
|
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||
| pioA: gpio@fffff400 { | ||
| compatible = "atmel,at91rm9200-gpio"; | ||
| reg = <0xfffff400 0x100>; | ||
| interrupts = <2 4>; | ||
| #gpio-cells = <2>; | ||
| gpio-controller; | ||
| }; | ||
|
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||
| pioB: gpio@fffff600 { | ||
| compatible = "atmel,at91rm9200-gpio"; | ||
| reg = <0xfffff600 0x100>; | ||
| interrupts = <2 4>; | ||
| #gpio-cells = <2>; | ||
| gpio-controller; | ||
| }; | ||
|
|
||
| pioC: gpio@fffff800 { | ||
| compatible = "atmel,at91rm9200-gpio"; | ||
| reg = <0xfffff800 0x100>; | ||
| interrupts = <3 4>; | ||
| #gpio-cells = <2>; | ||
| gpio-controller; | ||
| }; | ||
|
|
||
| pioD: gpio@fffffa00 { | ||
| compatible = "atmel,at91rm9200-gpio"; | ||
| reg = <0xfffffa00 0x100>; | ||
| interrupts = <3 4>; | ||
| #gpio-cells = <2>; | ||
| gpio-controller; | ||
| }; | ||
|
|
||
| dbgu: serial@fffff200 { | ||
| compatible = "atmel,at91sam9260-usart"; | ||
| reg = <0xfffff200 0x200>; | ||
| interrupts = <1 4>; | ||
| status = "disabled"; | ||
| }; | ||
|
|
||
| usart0: serial@f801c000 { | ||
| compatible = "atmel,at91sam9260-usart"; | ||
| reg = <0xf801c000 0x200>; | ||
| interrupts = <5 4>; | ||
| atmel,use-dma-rx; | ||
| atmel,use-dma-tx; | ||
| status = "disabled"; | ||
| }; | ||
|
|
||
| usart1: serial@f8020000 { | ||
| compatible = "atmel,at91sam9260-usart"; | ||
| reg = <0xf8020000 0x200>; | ||
| interrupts = <6 4>; | ||
| atmel,use-dma-rx; | ||
| atmel,use-dma-tx; | ||
| status = "disabled"; | ||
| }; | ||
|
|
||
| usart2: serial@f8024000 { | ||
| compatible = "atmel,at91sam9260-usart"; | ||
| reg = <0xf8024000 0x200>; | ||
| interrupts = <7 4>; | ||
| atmel,use-dma-rx; | ||
| atmel,use-dma-tx; | ||
| status = "disabled"; | ||
| }; | ||
|
|
||
| macb0: ethernet@f802c000 { | ||
| compatible = "cdns,at32ap7000-macb", "cdns,macb"; | ||
| reg = <0xf802c000 0x100>; | ||
| interrupts = <24 4>; | ||
| status = "disabled"; | ||
| }; | ||
|
|
||
| macb1: ethernet@f8030000 { | ||
| compatible = "cdns,at32ap7000-macb", "cdns,macb"; | ||
| reg = <0xf8030000 0x100>; | ||
| interrupts = <27 4>; | ||
| status = "disabled"; | ||
| }; | ||
| }; | ||
| }; | ||
| }; |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,14 @@ | ||
| /* | ||
| * at91sam9x5cm.dtsi - Device Tree Include file for AT91SAM9x5 CPU Module | ||
| * | ||
| * Copyright (C) 2012 Atmel, | ||
| * 2012 Nicolas Ferre <nicolas.ferre@atmel.com> | ||
| * | ||
| * Licensed under GPLv2 or later. | ||
| */ | ||
|
|
||
| / { | ||
| memory@20000000 { | ||
| reg = <0x20000000 0x8000000>; | ||
| }; | ||
| }; |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,2 +1,15 @@ | ||
| void sp804_clocksource_init(void __iomem *, const char *); | ||
| void __sp804_clocksource_and_sched_clock_init(void __iomem *, | ||
| const char *, int); | ||
|
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||
| static inline void sp804_clocksource_init(void __iomem *base, const char *name) | ||
| { | ||
| __sp804_clocksource_and_sched_clock_init(base, name, 0); | ||
| } | ||
|
|
||
| static inline void sp804_clocksource_and_sched_clock_init(void __iomem *base, | ||
| const char *name) | ||
| { | ||
| __sp804_clocksource_and_sched_clock_init(base, name, 1); | ||
| } | ||
|
|
||
| void sp804_clockevents_init(void __iomem *, unsigned int, const char *); |
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