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sh: Add support for SH7201 CPU subtype.
This patch adds support for the SH-2A FPU based SH7201 processor subtype. Signed-off-by: Peter Griffin <pgriffin@mpc-data.co.uk> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Peter Griffin
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Paul Mundt
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Dec 22, 2008
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/* | ||
* arch/sh/kernel/cpu/sh2a/clock-sh7201.c | ||
* | ||
* SH7201 support for the clock framework | ||
* | ||
* Copyright (C) 2008 Peter Griffin <pgriffin@mpc-data.co.uk> | ||
* | ||
* Based on clock-sh4.c | ||
* Copyright (C) 2005 Paul Mundt | ||
* | ||
* This file is subject to the terms and conditions of the GNU General Public | ||
* License. See the file "COPYING" in the main directory of this archive | ||
* for more details. | ||
*/ | ||
#include <linux/init.h> | ||
#include <linux/kernel.h> | ||
#include <asm/clock.h> | ||
#include <asm/freq.h> | ||
#include <asm/io.h> | ||
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const static int pll1rate[]={1,2,3,4,6,8}; | ||
const static int pfc_divisors[]={1,2,3,4,6,8,12}; | ||
#define ifc_divisors pfc_divisors | ||
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#if (CONFIG_SH_CLK_MD == 0) | ||
#define PLL2 (4) | ||
#elif (CONFIG_SH_CLK_MD == 2) | ||
#define PLL2 (2) | ||
#elif (CONFIG_SH_CLK_MD == 3) | ||
#define PLL2 (1) | ||
#else | ||
#error "Illegal Clock Mode!" | ||
#endif | ||
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static void master_clk_init(struct clk *clk) | ||
{ | ||
clk->rate = 10000000 * PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007]; | ||
} | ||
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static struct clk_ops sh7201_master_clk_ops = { | ||
.init = master_clk_init, | ||
}; | ||
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static void module_clk_recalc(struct clk *clk) | ||
{ | ||
int idx = (ctrl_inw(FREQCR) & 0x0007); | ||
clk->rate = clk->parent->rate / pfc_divisors[idx]; | ||
} | ||
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static struct clk_ops sh7201_module_clk_ops = { | ||
.recalc = module_clk_recalc, | ||
}; | ||
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static void bus_clk_recalc(struct clk *clk) | ||
{ | ||
int idx = (ctrl_inw(FREQCR) & 0x0007); | ||
clk->rate = clk->parent->rate / pfc_divisors[idx]; | ||
} | ||
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static struct clk_ops sh7201_bus_clk_ops = { | ||
.recalc = bus_clk_recalc, | ||
}; | ||
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static void cpu_clk_recalc(struct clk *clk) | ||
{ | ||
int idx = ((ctrl_inw(FREQCR) >> 4) & 0x0007); | ||
clk->rate = clk->parent->rate / ifc_divisors[idx]; | ||
} | ||
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static struct clk_ops sh7201_cpu_clk_ops = { | ||
.recalc = cpu_clk_recalc, | ||
}; | ||
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static struct clk_ops *sh7201_clk_ops[] = { | ||
&sh7201_master_clk_ops, | ||
&sh7201_module_clk_ops, | ||
&sh7201_bus_clk_ops, | ||
&sh7201_cpu_clk_ops, | ||
}; | ||
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void __init arch_init_clk_ops(struct clk_ops **ops, int idx) | ||
{ | ||
if (idx < ARRAY_SIZE(sh7201_clk_ops)) | ||
*ops = sh7201_clk_ops[idx]; | ||
} |
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