---

yaml
---
r: 318588
b: refs/heads/master
c: 12b0286
h: refs/heads/master
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: cc0f6398225ffd2b890ff83eafe212b1ae863cad
+refs/heads/master: 12b0286f49947a6cdc9285032d918466a8c3f5f9

trunk/drivers/gpu/drm/i915/i915_gem_context.c

@@ -324,6 +324,17 @@ mi_set_context(struct intel_ring_buffer *ring,
 {
 	int ret;
 
+	/* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
+	 * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
+	 * explicitly, so we rely on the value at ring init, stored in
+	 * itlb_before_ctx_switch.
+	 */
+	if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) {
+		ret = ring->flush(ring, 0, 0);
+		if (ret)
+			return ret;
+	}
+
 	ret = intel_ring_begin(ring, 6);
 	if (ret)
 		return ret;

trunk/drivers/gpu/drm/i915/intel_ringbuffer.c

@@ -423,6 +423,13 @@ static int init_render_ring(struct intel_ring_buffer *ring)
 		 */
 		I915_WRITE(CACHE_MODE_0,
 			   _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
+
+		/* This is not explicitly set for GEN6, so read the register.
+		 * see intel_ring_mi_set_context() for why we care.
+		 * TODO: consider explicitly setting the bit for GEN5
+		 */
+		ring->itlb_before_ctx_switch =
+			!!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
 	}
 
 	if (INTEL_INFO(dev)->gen >= 6)

trunk/drivers/gpu/drm/i915/intel_ringbuffer.h

@@ -116,6 +116,10 @@ struct  intel_ring_buffer {
 
 	wait_queue_head_t irq_queue;
 
+	/**
+	 * Do an explicit TLB flush before MI_SET_CONTEXT
+	 */
+	bool itlb_before_ctx_switch;
 	struct i915_hw_context *default_context;
 	struct drm_i915_gem_object *last_context_obj;