---

yaml --- r: 345199 b: refs/heads/master c: 572deb3 h: refs/heads/master i: 345197: a90879b 345195: 695fbfb 345191: 04e867c 345183: c46dbfd v: v3
git-mirror · Nov 11, 2012 · 28cd624 · 28cd624
1 parent 79da998
commit 28cd624
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Showing 2 changed files with 8 additions and 1 deletion.
diff --git a/[refs] b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: d74cf324e2b64349a49d0f17e9f6764f8a7d8349
+refs/heads/master: 572deb3728c1ad937d472b418588959344d884b4
diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c
@@ -3014,6 +3014,13 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 	/* For PCH output, training FDI link */
 	dev_priv->display.fdi_link_train(crtc);
 
+	/* XXX: pch pll's can be enabled any time before we enable the PCH
+	 * transcoder, and we actually should do this to not upset any PCH
+	 * transcoder that already use the clock when we share it.
+	 *
+	 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
+	 * unconditionally resets the pll - we need that to have the right LVDS
+	 * enable sequence. */
 	intel_enable_pch_pll(intel_crtc);
 
 	if (HAS_PCH_LPT(dev)) {