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---
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yaml
---
r: 166535
b: refs/heads/master
c: 210bed8
h: refs/heads/master
i:
  166533: 12fe4b3
  166531: b74d934
  166527: d5595d4
v: v3
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Alex Deucher authored and Dave Airlie committed Sep 25, 2009
1 parent 75a0e0b commit 2a4c961
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Showing 2 changed files with 6 additions and 6 deletions.
2 changes: 1 addition & 1 deletion [refs]
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Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 2b5d6c538b48772ba3351b8a8eed096f7af8de5d
refs/heads/master: 210bed8f827471e271f894fb99ee879a5d27cf30
10 changes: 5 additions & 5 deletions trunk/drivers/gpu/drm/radeon/r600_cs.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -380,7 +380,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
return -EINVAL;
}
ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
ib[idx+1] = upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
break;
case PACKET3_DRAW_INDEX_AUTO:
if (pkt->count != 1) {
Expand Down Expand Up @@ -408,7 +408,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
return -EINVAL;
}
ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
ib[idx+2] = upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
}
break;
case PACKET3_SURFACE_SYNC:
Expand Down Expand Up @@ -439,7 +439,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
return -EINVAL;
}
ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
ib[idx+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
}
break;
case PACKET3_EVENT_WRITE_EOP:
Expand All @@ -453,7 +453,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
return -EINVAL;
}
ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
ib[idx+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
break;
case PACKET3_SET_CONFIG_REG:
start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
Expand Down Expand Up @@ -575,7 +575,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
return -EINVAL;
}
ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
ib[idx+1+(i*7)+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
ib[idx+1+(i*7)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
break;
case SQ_TEX_VTX_INVALID_TEXTURE:
case SQ_TEX_VTX_INVALID_BUFFER:
Expand Down

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