---

yaml --- r: 323020 b: refs/heads/master c: 308b135 h: refs/heads/master v: v3
git-mirror · Sep 10, 2012 · 2c8cba4 · 2c8cba4
1 parent 82c9e8b
commit 2c8cba4
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diff --git a/[refs] b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 6d77987fe62eb97479f27426d12f33ef97145c5b
+refs/heads/master: 308b135e4fcc00c80c07e0e04e7afa8edf78583c
diff --git a/trunk/Documentation/i2c/busses/i2c-i801 b/trunk/Documentation/i2c/busses/i2c-i801
@@ -21,7 +21,6 @@ Supported adapters:
   * Intel DH89xxCC (PCH)
   * Intel Panther Point (PCH)
   * Intel Lynx Point (PCH)
-  * Intel Lynx Point-LP (PCH)
    Datasheets: Publicly available at the Intel website
 
 On Intel Patsburg and later chipsets, both the normal host SMBus controller

diff --git a/trunk/MAINTAINERS b/trunk/MAINTAINERS
@@ -3388,7 +3388,7 @@ M:	"Wolfram Sang (embedded platforms)" <w.sang@pengutronix.de>
 L:	linux-i2c@vger.kernel.org
 W:	http://i2c.wiki.kernel.org/
 T:	quilt kernel.org/pub/linux/kernel/people/jdelvare/linux-2.6/jdelvare-i2c/
-T:	git git://git.pengutronix.de/git/wsa/linux.git
+T:	git git://git.fluff.org/bjdooks/linux.git
 S:	Maintained
 F:	Documentation/i2c/
 F:	drivers/i2c/
@@ -3666,12 +3666,11 @@ F:	Documentation/networking/README.ipw2200
 F:	drivers/net/wireless/ipw2x00/
 
 INTEL(R) TRUSTED EXECUTION TECHNOLOGY (TXT)
-M:	Richard L Maliszewski <richard.l.maliszewski@intel.com>
-M:	Gang Wei <gang.wei@intel.com>
+M:	Joseph Cihula <joseph.cihula@intel.com>
 M:	Shane Wang <shane.wang@intel.com>
 L:	tboot-devel@lists.sourceforge.net
 W:	http://tboot.sourceforge.net
-T:	hg http://tboot.hg.sourceforge.net:8000/hgroot/tboot/tboot
+T:	Mercurial http://www.bughost.org/repos.hg/tboot.hg
 S:	Supported
 F:	Documentation/intel_txt.txt
 F:	include/linux/tboot.h

diff --git a/trunk/Makefile b/trunk/Makefile
@@ -1,7 +1,7 @@
 VERSION = 3
 PATCHLEVEL = 6
 SUBLEVEL = 0
-EXTRAVERSION = -rc6
+EXTRAVERSION = -rc5
 NAME = Saber-toothed Squirrel
 
 # *DOCUMENTATION*

diff --git a/trunk/arch/arm/Kconfig.debug b/trunk/arch/arm/Kconfig.debug
@@ -356,15 +356,15 @@ choice
 		  is nothing connected to read from the DCC.
 
 	config DEBUG_SEMIHOSTING
-		bool "Kernel low-level debug output via semihosting I/O"
+		bool "Kernel low-level debug output via semihosting I"
 		help
 		  Semihosting enables code running on an ARM target to use
 		  the I/O facilities on a host debugger/emulator through a
-		  simple SVC call. The host debugger or emulator must have
+		  simple SVC calls. The host debugger or emulator must have
 		  semihosting enabled for the special svc call to be trapped
 		  otherwise the kernel will crash.
 
-		  This is known to work with OpenOCD, as well as
+		  This is known to work with OpenOCD, as wellas
 		  ARM's Fast Models, or any other controlling environment
 		  that implements semihosting.
 

diff --git a/trunk/arch/arm/Makefile b/trunk/arch/arm/Makefile
@@ -284,10 +284,10 @@ zImage Image xipImage bootpImage uImage: vmlinux
 zinstall uinstall install: vmlinux
 	$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $@
 
-%.dtb: scripts
+%.dtb:
 	$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@
 
-dtbs: scripts
+dtbs:
 	$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@
 
 # We use MRPROPER_FILES and CLEAN_FILES now

diff --git a/trunk/arch/arm/boot/compressed/head.S b/trunk/arch/arm/boot/compressed/head.S
@@ -659,14 +659,10 @@ __armv7_mmu_cache_on:
 #ifdef CONFIG_CPU_ENDIAN_BE8
 		orr	r0, r0, #1 << 25	@ big-endian page tables
 #endif
-		mrcne   p15, 0, r6, c2, c0, 2   @ read ttb control reg
 		orrne	r0, r0, #1		@ MMU enabled
 		movne	r1, #0xfffffffd		@ domain 0 = client
-		bic     r6, r6, #1 << 31        @ 32-bit translation system
-		bic     r6, r6, #3 << 0         @ use only ttbr0
 		mcrne	p15, 0, r3, c2, c0, 0	@ load page table pointer
 		mcrne	p15, 0, r1, c3, c0, 0	@ load domain access control
-		mcrne   p15, 0, r6, c2, c0, 2   @ load ttb control
 #endif
 		mcr	p15, 0, r0, c7, c5, 4	@ ISB
 		mcr	p15, 0, r0, c1, c0, 0	@ load control register

diff --git a/trunk/arch/arm/boot/dts/at91sam9260.dtsi b/trunk/arch/arm/boot/dts/at91sam9260.dtsi
@@ -104,7 +104,6 @@
 				#gpio-cells = <2>;
 				gpio-controller;
 				interrupt-controller;
-				#interrupt-cells = <2>;
 			};
 
 			pioB: gpio@fffff600 {
@@ -114,7 +113,6 @@
 				#gpio-cells = <2>;
 				gpio-controller;
 				interrupt-controller;
-				#interrupt-cells = <2>;
 			};
 
 			pioC: gpio@fffff800 {
@@ -124,7 +122,6 @@
 				#gpio-cells = <2>;
 				gpio-controller;
 				interrupt-controller;
-				#interrupt-cells = <2>;
 			};
 
 			dbgu: serial@fffff200 {

diff --git a/trunk/arch/arm/boot/dts/at91sam9263.dtsi b/trunk/arch/arm/boot/dts/at91sam9263.dtsi
@@ -95,7 +95,6 @@
 				#gpio-cells = <2>;
 				gpio-controller;
 				interrupt-controller;
-				#interrupt-cells = <2>;
 			};
 
 			pioB: gpio@fffff400 {
@@ -105,7 +104,6 @@
 				#gpio-cells = <2>;
 				gpio-controller;
 				interrupt-controller;
-				#interrupt-cells = <2>;
 			};
 
 			pioC: gpio@fffff600 {
@@ -115,7 +113,6 @@
 				#gpio-cells = <2>;
 				gpio-controller;
 				interrupt-controller;
-				#interrupt-cells = <2>;
 			};
 
 			pioD: gpio@fffff800 {
@@ -125,7 +122,6 @@
 				#gpio-cells = <2>;
 				gpio-controller;
 				interrupt-controller;
-				#interrupt-cells = <2>;
 			};
 
 			pioE: gpio@fffffa00 {
@@ -135,7 +131,6 @@
 				#gpio-cells = <2>;
 				gpio-controller;
 				interrupt-controller;
-				#interrupt-cells = <2>;
 			};
 
 			dbgu: serial@ffffee00 {

diff --git a/trunk/arch/arm/boot/dts/at91sam9g45.dtsi b/trunk/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -113,7 +113,6 @@
 				#gpio-cells = <2>;
 				gpio-controller;
 				interrupt-controller;
-				#interrupt-cells = <2>;
 			};
 
 			pioB: gpio@fffff400 {
@@ -123,7 +122,6 @@
 				#gpio-cells = <2>;
 				gpio-controller;
 				interrupt-controller;
-				#interrupt-cells = <2>;
 			};
 
 			pioC: gpio@fffff600 {
@@ -133,7 +131,6 @@
 				#gpio-cells = <2>;
 				gpio-controller;
 				interrupt-controller;
-				#interrupt-cells = <2>;
 			};
 
 			pioD: gpio@fffff800 {
@@ -143,7 +140,6 @@
 				#gpio-cells = <2>;
 				gpio-controller;
 				interrupt-controller;
-				#interrupt-cells = <2>;
 			};
 
 			pioE: gpio@fffffa00 {
@@ -153,7 +149,6 @@
 				#gpio-cells = <2>;
 				gpio-controller;
 				interrupt-controller;
-				#interrupt-cells = <2>;
 			};
 
 			dbgu: serial@ffffee00 {

diff --git a/trunk/arch/arm/boot/dts/at91sam9n12.dtsi b/trunk/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -107,7 +107,6 @@
 				#gpio-cells = <2>;
 				gpio-controller;
 				interrupt-controller;
-				#interrupt-cells = <2>;
 			};
 
 			pioB: gpio@fffff600 {
@@ -117,7 +116,6 @@
 				#gpio-cells = <2>;
 				gpio-controller;
 				interrupt-controller;
-				#interrupt-cells = <2>;
 			};
 
 			pioC: gpio@fffff800 {
@@ -127,7 +125,6 @@
 				#gpio-cells = <2>;
 				gpio-controller;
 				interrupt-controller;
-				#interrupt-cells = <2>;
 			};
 
 			pioD: gpio@fffffa00 {
@@ -137,7 +134,6 @@
 				#gpio-cells = <2>;
 				gpio-controller;
 				interrupt-controller;
-				#interrupt-cells = <2>;
 			};
 
 			dbgu: serial@fffff200 {

diff --git a/trunk/arch/arm/boot/dts/at91sam9x5.dtsi b/trunk/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -115,7 +115,6 @@
 				#gpio-cells = <2>;
 				gpio-controller;
 				interrupt-controller;
-				#interrupt-cells = <2>;
 			};
 
 			pioB: gpio@fffff600 {
@@ -125,7 +124,6 @@
 				#gpio-cells = <2>;
 				gpio-controller;
 				interrupt-controller;
-				#interrupt-cells = <2>;
 			};
 
 			pioC: gpio@fffff800 {
@@ -135,7 +133,6 @@
 				#gpio-cells = <2>;
 				gpio-controller;
 				interrupt-controller;
-				#interrupt-cells = <2>;
 			};
 
 			pioD: gpio@fffffa00 {
@@ -145,7 +142,6 @@
 				#gpio-cells = <2>;
 				gpio-controller;
 				interrupt-controller;
-				#interrupt-cells = <2>;
 			};
 
 			dbgu: serial@fffff200 {

diff --git a/trunk/arch/arm/include/asm/assembler.h b/trunk/arch/arm/include/asm/assembler.h
@@ -320,12 +320,4 @@
 	.size \name , . - \name
 	.endm
 
-	.macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req
-#ifndef CONFIG_CPU_USE_DOMAINS
-	adds	\tmp, \addr, #\size - 1
-	sbcccs	\tmp, \tmp, \limit
-	bcs	\bad
-#endif
-	.endm
-
 #endif /* __ASM_ASSEMBLER_H__ */
diff --git a/trunk/arch/arm/include/asm/memory.h b/trunk/arch/arm/include/asm/memory.h
@@ -187,7 +187,6 @@ static inline unsigned long __phys_to_virt(unsigned long x)
 #define __phys_to_virt(x)	((x) - PHYS_OFFSET + PAGE_OFFSET)
 #endif
 #endif
-#endif /* __ASSEMBLY__ */
 
 #ifndef PHYS_OFFSET
 #ifdef PLAT_PHYS_OFFSET
@@ -197,8 +196,6 @@ static inline unsigned long __phys_to_virt(unsigned long x)
 #endif
 #endif
 
-#ifndef __ASSEMBLY__
-
 /*
  * PFNs are used to describe any physical page; this means
  * PFN 0 == physical address 0.

diff --git a/trunk/arch/arm/include/asm/tlb.h b/trunk/arch/arm/include/asm/tlb.h
@@ -199,17 +199,13 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
 {
 	pgtable_page_dtor(pte);
 
-#ifdef CONFIG_ARM_LPAE
-	tlb_add_flush(tlb, addr);
-#else
 	/*
 	 * With the classic ARM MMU, a pte page has two corresponding pmd
 	 * entries, each covering 1MB.
 	 */
 	addr &= PMD_MASK;
 	tlb_add_flush(tlb, addr + SZ_1M - PAGE_SIZE);
 	tlb_add_flush(tlb, addr + SZ_1M);
-#endif
 
 	tlb_remove_page(tlb, pte);
 }