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yaml --- r: 302428 b: refs/heads/master c: ba01a87 h: refs/heads/master v: v3
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Linus Torvalds
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May 22, 2012
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--- | ||
refs/heads/master: c52661d60f636d17e26ad834457db333bd1df494 | ||
refs/heads/master: ba01a87e37d3ca9efe141e2907c2ec3f89490b4f |
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What: ip_queue | ||
Date: finally removed in kernel v3.5.0 | ||
Contact: Pablo Neira Ayuso <pablo@netfilter.org> | ||
Description: | ||
ip_queue has been replaced by nfnetlink_queue which provides | ||
more advanced queueing mechanism to user-space. The ip_queue | ||
module was already announced to become obsolete years ago. | ||
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Users: |
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What: /sys/block/rssd*/registers | ||
Date: March 2012 | ||
KernelVersion: 3.3 | ||
Contact: Asai Thambi S P <asamymuthupa@micron.com> | ||
Description: This is a read-only file. Dumps below driver information and | ||
hardware registers. | ||
- S ACTive | ||
- Command Issue | ||
- Allocated | ||
- Completed | ||
- PORT IRQ STAT | ||
- HOST IRQ STAT | ||
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What: /sys/block/rssd*/status | ||
Date: April 2012 | ||
KernelVersion: 3.4 | ||
Contact: Asai Thambi S P <asamymuthupa@micron.com> | ||
Description: This is a read-only file. Indicates the status of the device. |
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What: /sys/bus/hsi | ||
Date: April 2012 | ||
KernelVersion: 3.4 | ||
Contact: Carlos Chinea <carlos.chinea@nokia.com> | ||
Description: | ||
High Speed Synchronous Serial Interface (HSI) is a | ||
serial interface mainly used for connecting application | ||
engines (APE) with cellular modem engines (CMT) in cellular | ||
handsets. | ||
The bus will be populated with devices (hsi_clients) representing | ||
the protocols available in the system. Bus drivers implement | ||
those protocols. | ||
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What: /sys/bus/hsi/devices/.../modalias | ||
Date: April 2012 | ||
KernelVersion: 3.4 | ||
Contact: Carlos Chinea <carlos.chinea@nokia.com> | ||
Description: Stores the same MODALIAS value emitted by uevent | ||
Format: hsi:<hsi_client device name> |
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What: /sys/block/<device>/iosched/target_latency | ||
Date: March 2012 | ||
contact: Tao Ma <boyu.mt@taobao.com> | ||
Description: | ||
The /sys/block/<device>/iosched/target_latency only exists | ||
when the user sets cfq to /sys/block/<device>/scheduler. | ||
It contains an estimated latency time for the cfq. cfq will | ||
use it to calculate the time slice used for every task. |
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27 changes: 27 additions & 0 deletions
27
trunk/Documentation/devicetree/bindings/arm/arch_timer.txt
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* ARM architected timer | ||
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ARM Cortex-A7 and Cortex-A15 have a per-core architected timer, which | ||
provides per-cpu timers. | ||
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The timer is attached to a GIC to deliver its per-processor interrupts. | ||
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** Timer node properties: | ||
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- compatible : Should at least contain "arm,armv7-timer". | ||
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- interrupts : Interrupt list for secure, non-secure, virtual and | ||
hypervisor timers, in that order. | ||
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- clock-frequency : The frequency of the main counter, in Hz. Optional. | ||
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Example: | ||
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timer { | ||
compatible = "arm,cortex-a15-timer", | ||
"arm,armv7-timer"; | ||
interrupts = <1 13 0xf08>, | ||
<1 14 0xf08>, | ||
<1 11 0xf08>, | ||
<1 10 0xf08>; | ||
clock-frequency = <100000000>; | ||
}; |
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127 changes: 127 additions & 0 deletions
127
trunk/Documentation/devicetree/bindings/net/mdio-mux-gpio.txt
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Properties for an MDIO bus multiplexer/switch controlled by GPIO pins. | ||
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This is a special case of a MDIO bus multiplexer. One or more GPIO | ||
lines are used to control which child bus is connected. | ||
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Required properties in addition to the generic multiplexer properties: | ||
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- compatible : mdio-mux-gpio. | ||
- gpios : GPIO specifiers for each GPIO line. One or more must be specified. | ||
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Example : | ||
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/* The parent MDIO bus. */ | ||
smi1: mdio@1180000001900 { | ||
compatible = "cavium,octeon-3860-mdio"; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
reg = <0x11800 0x00001900 0x0 0x40>; | ||
}; | ||
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/* | ||
An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a | ||
pair of GPIO lines. Child busses 2 and 3 populated with 4 | ||
PHYs each. | ||
*/ | ||
mdio-mux { | ||
compatible = "mdio-mux-gpio"; | ||
gpios = <&gpio1 3 0>, <&gpio1 4 0>; | ||
mdio-parent-bus = <&smi1>; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
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mdio@2 { | ||
reg = <2>; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
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phy11: ethernet-phy@1 { | ||
reg = <1>; | ||
compatible = "marvell,88e1149r"; | ||
marvell,reg-init = <3 0x10 0 0x5777>, | ||
<3 0x11 0 0x00aa>, | ||
<3 0x12 0 0x4105>, | ||
<3 0x13 0 0x0a60>; | ||
interrupt-parent = <&gpio>; | ||
interrupts = <10 8>; /* Pin 10, active low */ | ||
}; | ||
phy12: ethernet-phy@2 { | ||
reg = <2>; | ||
compatible = "marvell,88e1149r"; | ||
marvell,reg-init = <3 0x10 0 0x5777>, | ||
<3 0x11 0 0x00aa>, | ||
<3 0x12 0 0x4105>, | ||
<3 0x13 0 0x0a60>; | ||
interrupt-parent = <&gpio>; | ||
interrupts = <10 8>; /* Pin 10, active low */ | ||
}; | ||
phy13: ethernet-phy@3 { | ||
reg = <3>; | ||
compatible = "marvell,88e1149r"; | ||
marvell,reg-init = <3 0x10 0 0x5777>, | ||
<3 0x11 0 0x00aa>, | ||
<3 0x12 0 0x4105>, | ||
<3 0x13 0 0x0a60>; | ||
interrupt-parent = <&gpio>; | ||
interrupts = <10 8>; /* Pin 10, active low */ | ||
}; | ||
phy14: ethernet-phy@4 { | ||
reg = <4>; | ||
compatible = "marvell,88e1149r"; | ||
marvell,reg-init = <3 0x10 0 0x5777>, | ||
<3 0x11 0 0x00aa>, | ||
<3 0x12 0 0x4105>, | ||
<3 0x13 0 0x0a60>; | ||
interrupt-parent = <&gpio>; | ||
interrupts = <10 8>; /* Pin 10, active low */ | ||
}; | ||
}; | ||
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mdio@3 { | ||
reg = <3>; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
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phy21: ethernet-phy@1 { | ||
reg = <1>; | ||
compatible = "marvell,88e1149r"; | ||
marvell,reg-init = <3 0x10 0 0x5777>, | ||
<3 0x11 0 0x00aa>, | ||
<3 0x12 0 0x4105>, | ||
<3 0x13 0 0x0a60>; | ||
interrupt-parent = <&gpio>; | ||
interrupts = <12 8>; /* Pin 12, active low */ | ||
}; | ||
phy22: ethernet-phy@2 { | ||
reg = <2>; | ||
compatible = "marvell,88e1149r"; | ||
marvell,reg-init = <3 0x10 0 0x5777>, | ||
<3 0x11 0 0x00aa>, | ||
<3 0x12 0 0x4105>, | ||
<3 0x13 0 0x0a60>; | ||
interrupt-parent = <&gpio>; | ||
interrupts = <12 8>; /* Pin 12, active low */ | ||
}; | ||
phy23: ethernet-phy@3 { | ||
reg = <3>; | ||
compatible = "marvell,88e1149r"; | ||
marvell,reg-init = <3 0x10 0 0x5777>, | ||
<3 0x11 0 0x00aa>, | ||
<3 0x12 0 0x4105>, | ||
<3 0x13 0 0x0a60>; | ||
interrupt-parent = <&gpio>; | ||
interrupts = <12 8>; /* Pin 12, active low */ | ||
}; | ||
phy24: ethernet-phy@4 { | ||
reg = <4>; | ||
compatible = "marvell,88e1149r"; | ||
marvell,reg-init = <3 0x10 0 0x5777>, | ||
<3 0x11 0 0x00aa>, | ||
<3 0x12 0 0x4105>, | ||
<3 0x13 0 0x0a60>; | ||
interrupt-parent = <&gpio>; | ||
interrupts = <12 8>; /* Pin 12, active low */ | ||
}; | ||
}; | ||
}; |
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