Skip to content

Commit

Permalink
---
Browse files Browse the repository at this point in the history
yaml
---
r: 347772
b: refs/heads/master
c: d056a69
h: refs/heads/master
v: v3
  • Loading branch information
Will Deacon authored and Russell King committed Dec 20, 2012
1 parent 0c5bfa0 commit 30a081f
Show file tree
Hide file tree
Showing 2 changed files with 5 additions and 3 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 7bf9b7bef881aac820bf1f2e9951a17b09bd7e04
refs/heads/master: d056a699dd3d9366dd3b4d9996e7848209199cda
6 changes: 4 additions & 2 deletions trunk/arch/arm/mm/cache-v7.S
Original file line number Diff line number Diff line change
Expand Up @@ -44,8 +44,10 @@ ENDPROC(v7_flush_icache_all)
ENTRY(v7_flush_dcache_louis)
dmb @ ensure ordering with previous memory accesses
mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr
ands r3, r0, #0xe00000 @ extract LoUIS from clidr
mov r3, r3, lsr #20 @ r3 = LoUIS * 2
ALT_SMP(ands r3, r0, #(7 << 21)) @ extract LoUIS from clidr
ALT_UP(ands r3, r0, #(7 << 27)) @ extract LoUU from clidr
ALT_SMP(mov r3, r3, lsr #20) @ r3 = LoUIS * 2
ALT_UP(mov r3, r3, lsr #26) @ r3 = LoUU * 2
moveq pc, lr @ return if level == 0
mov r10, #0 @ r10 (starting level) = 0
b flush_levels @ start flushing cache levels
Expand Down

0 comments on commit 30a081f

Please sign in to comment.