---

yaml
---
r: 31251
b: refs/heads/master
c: a2c2bc4
h: refs/heads/master
i:
  31249: b7624ca
  31247: 1adddf8
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 86165879a20753e7ed86be4c2e9bba3f32ed0aff
+refs/heads/master: a2c2bc4b263828a380813a236fa6fcf8185b460b

trunk/arch/mips/mm/sc-mips.c

@@ -24,45 +24,15 @@
  */
 static void mips_sc_wback_inv(unsigned long addr, unsigned long size)
 {
-	unsigned long sc_lsize = cpu_scache_line_size();
-	unsigned long end, a;
-
-	pr_debug("mips_sc_wback_inv[%08lx,%08lx]", addr, size);
-
-	/* Catch bad driver code */
-	BUG_ON(size == 0);
-
-	a = addr & ~(sc_lsize - 1);
-	end = (addr + size - 1) & ~(sc_lsize - 1);
-	while (1) {
-		flush_scache_line(a);		/* Hit_Writeback_Inv_SD */
-		if (a == end)
-			break;
-		a += sc_lsize;
-	}
+	blast_scache_range(addr, addr + size);
 }
 
 /*
  * Invalidate the secondary cache before DMA.
  */
 static void mips_sc_inv(unsigned long addr, unsigned long size)
 {
-	unsigned long sc_lsize = cpu_scache_line_size();
-	unsigned long end, a;
-
-	pr_debug("mips_sc_inv[%08lx,%08lx]", addr, size);
-
-	/* Catch bad driver code */
-	BUG_ON(size == 0);
-
-	a = addr & ~(sc_lsize - 1);
-	end = (addr + size - 1) & ~(sc_lsize - 1);
-	while (1) {
-		invalidate_scache_line(a);	/* Hit_Invalidate_SD */
-		if (a == end)
-			break;
-		a += sc_lsize;
-	}
+	blast_inv_scache_range(addr, addr + size);
 }
 
 static void mips_sc_enable(void)
@@ -123,6 +93,7 @@ static inline int __init mips_sc_probe(void)
 		return 0;
 
 	c->scache.waysize = c->scache.sets * c->scache.linesz;
+	c->scache.waybit = __ffs(c->scache.waysize);
 
 	c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;