---

yaml --- r: 127131 b: refs/heads/master c: a0dcfb1 h: refs/heads/master i: 127129: 9bc8381 127127: 8e82afa v: v3
git-mirror · Jan 7, 2009 · 31a93fe · 31a93fe
1 parent aa70166
commit 31a93fe
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Showing 4 changed files with 14 additions and 7 deletions.
diff --git a/[refs] b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 7419a327f6264bef869b195497aaf03b72ca17b7
+refs/heads/master: a0dcfb16e606ca095eb1e9e789aff5e41e9adb1a
diff --git a/trunk/arch/blackfin/mach-bf533/include/mach/blackfin.h b/trunk/arch/blackfin/mach-bf533/include/mach/blackfin.h
@@ -44,6 +44,13 @@
 
 #define BFIN_UART_NR_PORTS      1
 
+#define CH_UART_RX CH_UART0_RX
+#define CH_UART_TX CH_UART0_TX
+
+#define IRQ_UART_ERROR IRQ_UART0_ERROR
+#define IRQ_UART_RX    IRQ_UART0_RX
+#define IRQ_UART_TX    IRQ_UART0_TX
+
 #define OFFSET_THR              0x00	/* Transmit Holding register            */
 #define OFFSET_RBR              0x00	/* Receive Buffer register              */
 #define OFFSET_DLL              0x00	/* Divisor Latch (Low-Byte)             */

diff --git a/trunk/arch/blackfin/mach-bf533/include/mach/dma.h b/trunk/arch/blackfin/mach-bf533/include/mach/dma.h
@@ -16,8 +16,8 @@
 #define CH_SPORT1_RX    3
 #define CH_SPORT1_TX    4
 #define CH_SPI          5
-#define CH_UART_RX      6
-#define CH_UART_TX      7
+#define CH_UART0_RX     6
+#define CH_UART0_TX     7
 #define CH_MEM_STREAM0_DEST     8	 /* TX */
 #define CH_MEM_STREAM0_SRC      9	 /* RX */
 #define CH_MEM_STREAM1_DEST     10	 /* TX */

diff --git a/trunk/arch/blackfin/mach-bf533/include/mach/irq.h b/trunk/arch/blackfin/mach-bf533/include/mach/irq.h
@@ -90,16 +90,16 @@ Core        Emulation               **
 #define	IRQ_SPORT0_ERROR	10	/*SPORT0 Error Interrupt */
 #define	IRQ_SPORT1_ERROR	11	/*SPORT1 Error Interrupt */
 #define	IRQ_SPI_ERROR		12	/*SPI Error Interrupt */
-#define	IRQ_UART_ERROR		13	/*UART Error Interrupt */
+#define	IRQ_UART0_ERROR		13	/*UART Error Interrupt */
 #define	IRQ_RTC			14	/*RTC Interrupt */
 #define	IRQ_PPI			15	/*DMA0 Interrupt (PPI) */
 #define	IRQ_SPORT0_RX		16	/*DMA1 Interrupt (SPORT0 RX) */
 #define	IRQ_SPORT0_TX		17	/*DMA2 Interrupt (SPORT0 TX) */
 #define	IRQ_SPORT1_RX		18	/*DMA3 Interrupt (SPORT1 RX) */
 #define	IRQ_SPORT1_TX		19	/*DMA4 Interrupt (SPORT1 TX) */
-#define 	IRQ_SPI			20	/*DMA5 Interrupt (SPI) */
-#define	IRQ_UART_RX		21	/*DMA6 Interrupt (UART RX) */
-#define	IRQ_UART_TX		22	/*DMA7 Interrupt (UART TX) */
+#define	IRQ_SPI			20	/*DMA5 Interrupt (SPI) */
+#define	IRQ_UART0_RX		21	/*DMA6 Interrupt (UART RX) */
+#define	IRQ_UART0_TX		22	/*DMA7 Interrupt (UART TX) */
 #define	IRQ_TMR0		23	/*Timer 0 */
 #define	IRQ_TMR1		24	/*Timer 1 */
 #define	IRQ_TMR2		25	/*Timer 2 */