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Santosh Shilimkar
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Kevin Hilman
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Dec 8, 2011
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| --- | ||
| refs/heads/master: fcf6efa3ffbc3cc19e7abe39e0b90f497df2fc42 | ||
| refs/heads/master: b2b9762f76981c16a8768255284efeae7f27e4f1 |
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| /* | ||
| * OMAP MPUSS low power code | ||
| * | ||
| * Copyright (C) 2011 Texas Instruments, Inc. | ||
| * Santosh Shilimkar <santosh.shilimkar@ti.com> | ||
| * | ||
| * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU | ||
| * Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller, | ||
| * CPU0 and CPU1 LPRM modules. | ||
| * CPU0, CPU1 and MPUSS each have there own power domain and | ||
| * hence multiple low power combinations of MPUSS are possible. | ||
| * | ||
| * The CPU0 and CPU1 can't support Closed switch Retention (CSWR) | ||
| * because the mode is not supported by hw constraints of dormant | ||
| * mode. While waking up from the dormant mode, a reset signal | ||
| * to the Cortex-A9 processor must be asserted by the external | ||
| * power controller. | ||
| * | ||
| * With architectural inputs and hardware recommendations, only | ||
| * below modes are supported from power gain vs latency point of view. | ||
| * | ||
| * CPU0 CPU1 MPUSS | ||
| * ---------------------------------------------- | ||
| * ON ON ON | ||
| * ON(Inactive) OFF ON(Inactive) | ||
| * OFF OFF CSWR | ||
| * OFF OFF OSWR (*TBD) | ||
| * OFF OFF OFF* (*TBD) | ||
| * ---------------------------------------------- | ||
| * | ||
| * Note: CPU0 is the master core and it is the last CPU to go down | ||
| * and first to wake-up when MPUSS low power states are excercised | ||
| * | ||
| * | ||
| * This program is free software; you can redistribute it and/or modify | ||
| * it under the terms of the GNU General Public License version 2 as | ||
| * published by the Free Software Foundation. | ||
| */ | ||
|
|
||
| #include <linux/kernel.h> | ||
| #include <linux/io.h> | ||
| #include <linux/errno.h> | ||
| #include <linux/linkage.h> | ||
| #include <linux/smp.h> | ||
|
|
||
| #include <asm/cacheflush.h> | ||
| #include <asm/tlbflush.h> | ||
| #include <asm/smp_scu.h> | ||
| #include <asm/system.h> | ||
| #include <asm/pgalloc.h> | ||
| #include <asm/suspend.h> | ||
|
|
||
| #include <plat/omap44xx.h> | ||
|
|
||
| #include "common.h" | ||
| #include "omap4-sar-layout.h" | ||
| #include "pm.h" | ||
| #include "powerdomain.h" | ||
|
|
||
| #ifdef CONFIG_SMP | ||
|
|
||
| struct omap4_cpu_pm_info { | ||
| struct powerdomain *pwrdm; | ||
| void __iomem *scu_sar_addr; | ||
| void __iomem *wkup_sar_addr; | ||
| }; | ||
|
|
||
| static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info); | ||
|
|
||
| /* | ||
| * Program the wakeup routine address for the CPU0 and CPU1 | ||
| * used for OFF or DORMANT wakeup. | ||
| */ | ||
| static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr) | ||
| { | ||
| struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); | ||
|
|
||
| __raw_writel(addr, pm_info->wkup_sar_addr); | ||
| } | ||
|
|
||
| /* | ||
| * Set the CPUx powerdomain's previous power state | ||
| */ | ||
| static inline void set_cpu_next_pwrst(unsigned int cpu_id, | ||
| unsigned int power_state) | ||
| { | ||
| struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); | ||
|
|
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| pwrdm_set_next_pwrst(pm_info->pwrdm, power_state); | ||
| } | ||
|
|
||
| /* | ||
| * Read CPU's previous power state | ||
| */ | ||
| static inline unsigned int read_cpu_prev_pwrst(unsigned int cpu_id) | ||
| { | ||
| struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); | ||
|
|
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| return pwrdm_read_prev_pwrst(pm_info->pwrdm); | ||
| } | ||
|
|
||
| /* | ||
| * Clear the CPUx powerdomain's previous power state | ||
| */ | ||
| static inline void clear_cpu_prev_pwrst(unsigned int cpu_id) | ||
| { | ||
| struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); | ||
|
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| pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); | ||
| } | ||
|
|
||
| /* | ||
| * Store the SCU power status value to scratchpad memory | ||
| */ | ||
| static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state) | ||
| { | ||
| struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); | ||
| u32 scu_pwr_st; | ||
|
|
||
| switch (cpu_state) { | ||
| case PWRDM_POWER_RET: | ||
| scu_pwr_st = SCU_PM_DORMANT; | ||
| break; | ||
| case PWRDM_POWER_OFF: | ||
| scu_pwr_st = SCU_PM_POWEROFF; | ||
| break; | ||
| case PWRDM_POWER_ON: | ||
| case PWRDM_POWER_INACTIVE: | ||
| default: | ||
| scu_pwr_st = SCU_PM_NORMAL; | ||
| break; | ||
| } | ||
|
|
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| __raw_writel(scu_pwr_st, pm_info->scu_sar_addr); | ||
| } | ||
|
|
||
| /** | ||
| * omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function | ||
| * The purpose of this function is to manage low power programming | ||
| * of OMAP4 MPUSS subsystem | ||
| * @cpu : CPU ID | ||
| * @power_state: Low power state. | ||
| */ | ||
| int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state) | ||
| { | ||
| unsigned int save_state = 0; | ||
| unsigned int wakeup_cpu; | ||
|
|
||
| if (omap_rev() == OMAP4430_REV_ES1_0) | ||
| return -ENXIO; | ||
|
|
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| switch (power_state) { | ||
| case PWRDM_POWER_ON: | ||
| case PWRDM_POWER_INACTIVE: | ||
| save_state = 0; | ||
| break; | ||
| case PWRDM_POWER_OFF: | ||
| save_state = 1; | ||
| break; | ||
| case PWRDM_POWER_RET: | ||
| default: | ||
| /* | ||
| * CPUx CSWR is invalid hardware state. Also CPUx OSWR | ||
| * doesn't make much scense, since logic is lost and $L1 | ||
| * needs to be cleaned because of coherency. This makes | ||
| * CPUx OSWR equivalent to CPUX OFF and hence not supported | ||
| */ | ||
| WARN_ON(1); | ||
| return -ENXIO; | ||
| } | ||
|
|
||
| clear_cpu_prev_pwrst(cpu); | ||
| set_cpu_next_pwrst(cpu, power_state); | ||
| set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume)); | ||
| scu_pwrst_prepare(cpu, power_state); | ||
|
|
||
| /* | ||
| * Call low level function with targeted low power state. | ||
| */ | ||
| cpu_suspend(save_state, omap4_finish_suspend); | ||
|
|
||
| /* | ||
| * Restore the CPUx power state to ON otherwise CPUx | ||
| * power domain can transitions to programmed low power | ||
| * state while doing WFI outside the low powe code. On | ||
| * secure devices, CPUx does WFI which can result in | ||
| * domain transition | ||
| */ | ||
| wakeup_cpu = smp_processor_id(); | ||
| set_cpu_next_pwrst(wakeup_cpu, PWRDM_POWER_ON); | ||
|
|
||
| return 0; | ||
| } | ||
|
|
||
| /* | ||
| * Initialise OMAP4 MPUSS | ||
| */ | ||
| int __init omap4_mpuss_init(void) | ||
| { | ||
| struct omap4_cpu_pm_info *pm_info; | ||
| void __iomem *sar_base = omap4_get_sar_ram_base(); | ||
|
|
||
| if (omap_rev() == OMAP4430_REV_ES1_0) { | ||
| WARN(1, "Power Management not supported on OMAP4430 ES1.0\n"); | ||
| return -ENODEV; | ||
| } | ||
|
|
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| /* Initilaise per CPU PM information */ | ||
| pm_info = &per_cpu(omap4_pm_info, 0x0); | ||
| pm_info->scu_sar_addr = sar_base + SCU_OFFSET0; | ||
| pm_info->wkup_sar_addr = sar_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET; | ||
| pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm"); | ||
| if (!pm_info->pwrdm) { | ||
| pr_err("Lookup failed for CPU0 pwrdm\n"); | ||
| return -ENODEV; | ||
| } | ||
|
|
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| /* Clear CPU previous power domain state */ | ||
| pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); | ||
|
|
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| /* Initialise CPU0 power domain state to ON */ | ||
| pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); | ||
|
|
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| pm_info = &per_cpu(omap4_pm_info, 0x1); | ||
| pm_info->scu_sar_addr = sar_base + SCU_OFFSET1; | ||
| pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET; | ||
| pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm"); | ||
| if (!pm_info->pwrdm) { | ||
| pr_err("Lookup failed for CPU1 pwrdm\n"); | ||
| return -ENODEV; | ||
| } | ||
|
|
||
| /* Clear CPU previous power domain state */ | ||
| pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); | ||
|
|
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| /* Initialise CPU1 power domain state to ON */ | ||
| pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); | ||
|
|
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| /* Save device type on scratchpad for low level code to use */ | ||
| if (omap_type() != OMAP2_DEVICE_TYPE_GP) | ||
| __raw_writel(1, sar_base + OMAP_TYPE_OFFSET); | ||
| else | ||
| __raw_writel(0, sar_base + OMAP_TYPE_OFFSET); | ||
|
|
||
| return 0; | ||
| } | ||
|
|
||
| #endif |
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