Skip to content

Commit

Permalink
---
Browse files Browse the repository at this point in the history 
yaml
---
r: 372239
b: refs/heads/master
c: 1c8408e
h: refs/heads/master
i:
  372237: 2fe7323
  372235: 34639ed
  372231: e7e5d9d
  372223: 06d7e41
v: v3
  • Loading branch information
Heiko Stuebner authored and Kukjin Kim committed Mar 5, 2013
1 parent a391c76 commit 358ba19
Show file tree
Hide file tree
Showing 4 changed files with 45 additions and 84 deletions.
2 changes: 1 addition & 1 deletion [refs]
View file
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 9eecbe509607265d28d76b39bc479f01b6d55e01
refs/heads/master: 1c8408e3137bcb78d9ab8af832111f455d11e99c
4 changes: 4 additions & 0 deletions trunk/arch/arm/mach-s3c24xx/include/mach/irqs.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -59,6 +59,10 @@
#define IRQ_ADCPARENT S3C2410_IRQ(31)

/* interrupts generated from the external interrupts sources */
#define IRQ_EINT0_2412 S3C2410_IRQ(32)
#define IRQ_EINT1_2412 S3C2410_IRQ(33)
#define IRQ_EINT2_2412 S3C2410_IRQ(34)
#define IRQ_EINT3_2412 S3C2410_IRQ(35)
#define IRQ_EINT4 S3C2410_IRQ(36) /* 52 */
#define IRQ_EINT5 S3C2410_IRQ(37)
#define IRQ_EINT6 S3C2410_IRQ(38)
Expand Down
118 changes: 36 additions & 82 deletions trunk/arch/arm/mach-s3c24xx/irq.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -342,7 +342,10 @@ static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
case S3C_IRQTYPE_NONE:
return 0;
case S3C_IRQTYPE_EINT:
if (irq_data->parent_irq)
/* On the S3C2412, the EINT0to3 have a parent irq
* but need the s3c_irq_eint0t4 chip
*/
if (irq_data->parent_irq && (!soc_is_s3c2412() || hw >= 4))
irq_set_chip_and_handler(virq, &s3c_irqext_chip,
handle_edge_irq);
else
Expand Down Expand Up @@ -623,10 +626,10 @@ void __init s3c24xx_init_irq(void)

#ifdef CONFIG_CPU_S3C2412
static struct s3c_irq_data init_s3c2412base[32] = {
{ .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
{ .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
{ .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
{ .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT0 */
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT1 */
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT2 */
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT3 */
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
{ .type = S3C_IRQTYPE_NONE, }, /* reserved */
Expand Down Expand Up @@ -657,6 +660,33 @@ static struct s3c_irq_data init_s3c2412base[32] = {
{ .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
};

static struct s3c_irq_data init_s3c2412eint[32] = {
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 0 }, /* EINT0 */
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 1 }, /* EINT1 */
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 2 }, /* EINT2 */
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 3 }, /* EINT3 */
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
};

static struct s3c_irq_data init_s3c2412subint[32] = {
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
Expand All @@ -675,77 +705,9 @@ static struct s3c_irq_data init_s3c2412subint[32] = {
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* CF */
};

/* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by
* having them turn up in both the INT* and the EINT* registers. Whilst
* both show the status, they both now need to be acked when the IRQs
* go off.
*/

static void
s3c2412_irq_mask(struct irq_data *data)
{
unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
unsigned long mask;

mask = __raw_readl(S3C2410_INTMSK);
__raw_writel(mask | bitval, S3C2410_INTMSK);

mask = __raw_readl(S3C2412_EINTMASK);
__raw_writel(mask | bitval, S3C2412_EINTMASK);
}

static inline void
s3c2412_irq_ack(struct irq_data *data)
{
unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);

__raw_writel(bitval, S3C2412_EINTPEND);
__raw_writel(bitval, S3C2410_SRCPND);
__raw_writel(bitval, S3C2410_INTPND);
}

static inline void
s3c2412_irq_maskack(struct irq_data *data)
{
unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
unsigned long mask;

mask = __raw_readl(S3C2410_INTMSK);
__raw_writel(mask|bitval, S3C2410_INTMSK);

mask = __raw_readl(S3C2412_EINTMASK);
__raw_writel(mask | bitval, S3C2412_EINTMASK);

__raw_writel(bitval, S3C2412_EINTPEND);
__raw_writel(bitval, S3C2410_SRCPND);
__raw_writel(bitval, S3C2410_INTPND);
}

static void
s3c2412_irq_unmask(struct irq_data *data)
{
unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
unsigned long mask;

mask = __raw_readl(S3C2412_EINTMASK);
__raw_writel(mask & ~bitval, S3C2412_EINTMASK);

mask = __raw_readl(S3C2410_INTMSK);
__raw_writel(mask & ~bitval, S3C2410_INTMSK);
}

static struct irq_chip s3c2412_irq_eint0t4 = {
.irq_ack = s3c2412_irq_ack,
.irq_mask = s3c2412_irq_mask,
.irq_unmask = s3c2412_irq_unmask,
.irq_set_wake = s3c_irq_wake,
.irq_set_type = s3c_irqext_type,
};

void s3c2412_init_irq(void)
{
struct s3c_irq_intc *main_intc;
unsigned int irqno;

pr_info("S3C2412: IRQ Support\n");

Expand All @@ -759,16 +721,8 @@ void s3c2412_init_irq(void)
return;
}

s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
s3c24xx_init_intc(NULL, &init_s3c2412eint[0], main_intc, 0x560000a4);
s3c24xx_init_intc(NULL, &init_s3c2412subint[0], main_intc, 0x4a000018);

/* special handling for eints 0 to 3 */

for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4,
handle_edge_irq);
set_irq_flags(irqno, IRQF_VALID);
}
}
#endif

Expand Down
5 changes: 4 additions & 1 deletion trunk/drivers/gpio/gpio-samsung.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1123,7 +1123,10 @@ int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset)
{
if (offset < 4)
return IRQ_EINT0 + offset;
if (soc_is_s3c2412())
return IRQ_EINT0_2412 + offset;
else
return IRQ_EINT0 + offset;

if (offset < 8)
return IRQ_EINT4 + offset - 4;
Expand Down

0 comments on commit 358ba19

Please sign in to comment.