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Blackfin: fix MPU handling of invalid memory accesses
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The protect_page() function was incorrectly setting up the hardware tables
based on possible access capabilities rather than the actual requested
values.  This means we would grant more access to mmap-ed pages than we
should have.  Once we fix this, we need to tweak the signal generated by
such accesses to aline ourselves with other ports.  This allows the LTP
mmap0{5,6,7} cases to run properly.

Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Graf Yang authored and Mike Frysinger committed Sep 17, 2009
1 parent 8fc4dd9 commit 36b8412
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Showing 2 changed files with 4 additions and 4 deletions.
6 changes: 3 additions & 3 deletions arch/blackfin/include/asm/mmu_context.h
Original file line number Diff line number Diff line change
Expand Up @@ -127,17 +127,17 @@ static inline void protect_page(struct mm_struct *mm, unsigned long addr,
unsigned long idx = page >> 5;
unsigned long bit = 1 << (page & 31);

if (flags & VM_MAYREAD)
if (flags & VM_READ)
mask[idx] |= bit;
else
mask[idx] &= ~bit;
mask += page_mask_nelts;
if (flags & VM_MAYWRITE)
if (flags & VM_WRITE)
mask[idx] |= bit;
else
mask[idx] &= ~bit;
mask += page_mask_nelts;
if (flags & VM_MAYEXEC)
if (flags & VM_EXEC)
mask[idx] |= bit;
else
mask[idx] &= ~bit;
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2 changes: 1 addition & 1 deletion arch/blackfin/kernel/traps.c
Original file line number Diff line number Diff line change
Expand Up @@ -411,7 +411,7 @@ asmlinkage void trap_c(struct pt_regs *fp)
/* 0x23 - Data CPLB protection violation, handled here */
case VEC_CPLB_VL:
info.si_code = ILL_CPLB_VI;
sig = SIGBUS;
sig = SIGSEGV;
strerror = KERN_NOTICE EXC_0x23(KERN_NOTICE);
CHK_DEBUGGER_TRAP_MAYBE();
break;
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